upipe_handshake_Template.v

Post date: Mar 28, 2011 2:46:31 PM

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Company: 

// Engineer: 

// 

// Create Date:    05:10:11 11/05/2010 

// Design Name: 

// Module Name:    upipe 

// Project Name: 

// Target Devices: 

// Tool versions: 

// Description: 

//

// Dependencies: 

//

// Revision: 

// Revision 0.01 - File Created

// Additional Comments: 

//

//////////////////////////////////////////////////////////////////////////////////

module uproc #(parameter WIDTH=32)(

   input reset,

   input start

   );

// Handshake signals

(* keep *) wire Req_PC, Ack_PC,  DReq_PC;

(* keep *) wire Req_IF, DReq_IF, Ack_IF;

(* keep *) wire Req_ID, DReq_ID, Ack_ID;

(* keep *) wire Req_EX, DReq_EX, Ack_EX;

(* keep *) wire Req_M,  DReq_M,  Ack_M;

(* keep *) wire Req_WB, DReq_WB, Ack_WB;

// Local clocks

// set attributes "CLOCK_SIGNAL" and "USELOWSKEWLINES"

wire lt_PC, lt_IF, lt_ID, lt_EX, lt_M, lt_WB;

//------------------------------------------------------------------------------------------------------------------

// Start signal ----------------------------------------------------------------------------------------------------

assign Req_PC = start & !DReq_PC;

//------------------------------------------------------------------------------------------------------------------

//------------------------------------------------------------------------------------------------------------------

// Program Counter Update ------------------------------------------------------------------------------------------

//------------------------------------------------------------------------------------------------------------------

delayLUT8 D_PC(.in(Ack_PC), .out(DReq_PC));

LatchCtrl lc_PC (.reset(reset), .Ri(Req_PC), .Ai(Ack_IF), .Ro(Req_IF), .Ao(Ack_PC));

// synthesis attribute CLOCK_SIGNAL lt_PC YES

// synthesis attribute USELOWSKEWLINES lt_PC YES

assign lt_PC = Req_IF;

//------------------------------------------------------------------------------------------------------------------

// Instruction Fetch      ------------------------------------------------------------------------------------------

//------------------------------------------------------------------------------------------------------------------

delayLUT8 D_IF (.in(Req_IF), .out(DReq_IF));

LatchCtrl lc_IF (.reset(reset), .Ri(DReq_IF), .Ai(Ack_ID), .Ro(Req_ID), .Ao(Ack_IF));

// synthesis attribute CLOCK_SIGNAL lt_IF YES

// synthesis attribute USELOWSKEWLINES lt_IF YES

assign lt_IF = Req_ID;

//------------------------------------------------------------------------------------------------------------------

// Instruction Decode     ------------------------------------------------------------------------------------------

//------------------------------------------------------------------------------------------------------------------

delayLUT8 D_ID (.in(Req_ID), .out(DReq_ID));

LatchCtrl lc_ID (.reset(reset), .Ri(DReq_ID), .Ai(Ack_EX), .Ro(Req_EX), .Ao(Ack_ID));

// synthesis attribute CLOCK_SIGNAL lt_ID YES

// synthesis attribute USELOWSKEWLINES lt_ID YES

assign lt_ID = Req_EX;

//------------------------------------------------------------------------------------------------------------------

// Instruction Exe        ------------------------------------------------------------------------------------------

//------------------------------------------------------------------------------------------------------------------

delayLUT8 D_EX (.in(Req_EX), .out(DReq_EX));

LatchCtrl lc_EX (.reset(reset), .Ri(DReq_EX), .Ai(Ack_M), .Ro(Req_M), .Ao(Ack_EX));

// synthesis attribute CLOCK_SIGNAL lt_EX YES

// synthesis attribute USELOWSKEWLINES lt_EX YES

assign lt_EX = Req_M;

//------------------------------------------------------------------------------------------------------------------

// Instruction MEM        ------------------------------------------------------------------------------------------

//------------------------------------------------------------------------------------------------------------------

delayLUT8 D_M (.in(Req_M), .out(DReq_M));

LatchCtrl lc_M (.reset(reset), .Ri(DReq_M), .Ai(Ack_WB), .Ro(Req_WB), .Ao(Ack_M));

// synthesis attribute CLOCK_SIGNAL lt_M YES

// synthesis attribute USELOWSKEWLINES lt_M YES

assign lt_M = Req_WB;

endmodule

// Single stage for Control Path

module LatchCtrl(

   input reset,

   input Ri,

input Ai,

output Ro,

output Ao

);

wire lt, Latch_delayed;

   // Simple uPipelined Stage Logic

   Cgate cgate_inst1 (.a(Ri), .b(Latch_delayed), .reset(reset), .out(lt));

   Cgate cgate_inst2 (.a(lt), .b(Ai), .reset(reset), .out(Latch));

delayLUT1 delay(.in(Latch), .out(Latch_delayed));

assign Ro = Latch;

assign Ao = lt;

endmodule