論文發表

Journal Papers:

• 1. Chung-Yi Li, Hong-Chi Hu, Yuan-Ho Chen*, and Shinn-Yn Lin, “Low-latency and Power-efficient Row-based Binary-Weighted Compensator for Fixed-Width Booth Multiplier,” International Journal of Circuit Theory and Applications, vol. 53, pp. 2409- 2426, April 2025. (SCI)

  2. Yuan-Ho Chen, Che-An Chou, Chin-Fu Nien*, and Shinn-Yn Lin, “Design and Implementation of a Very-Large-Scale Integration–Based Annealing Accelerator for Efficiently Solving Combinatorial Optimization Problems,” IEEE Trans. Circuits Syst. II, vol. 71, pp. 4291- 4295, 2024. (SCI)

  3. Yuan-Ho Chen, Hsin-Tung Hua, Chin-Fu Nien*, and Shinn-Yn Lin, “VLSI Implementation of an Annealing Accelerator for Solving Combinatorial Optimization Problems,” IEEE Nanotechnology Magazine, vol. 18, pp. 23-30, 2024. (SCI)

  4. Yuan-Ho Chen, Szi-Wen Chen*, Hong-Wen Jian, Shinn-Yn Lin, and Rou-Shayn Chen, “A Very Large-Scale Integration (VLSI) Chip Design for Abnormal Heartbeat Detection Using a Data-Shifting Neural Network (DSNN),” IEEE Access, vol. 12, pp. 14005 - 14013, 2024. (SCI) 

  5. Yuan-Ho Chen, Ching-Tien Wang, Shinn-Yn Lin, Chao-Sung Lai*, and Bing Sheu, “Artificial Intelligence Chip Design for High-Speed Cardiac Arrhythmia Classification,” IEEE Nanotechnology Magazine, vol. 17, pp. 29-35, 2023. (SCI)

  6. Yuan-Ho Chen, Chih-Wen Lu*, Szi-Wen Chen*, Ming-Han Tsai, Shinn-Yn Lin, and Rou-Shayn Chen, “VLSI Implementation of QRS Complex Detector Based on Wavelet Decomposition,” IEEE Access, vol. 10, pp. 134758 - 134768, Dec. 2022. (SCI)

  7. Yuan-Ho Chen, Szi-Wen Chen*, Pei-Jung Chang, Hsin-Tung Hua, Shinn-Yn Lin, and Rou-Shayn Chen, “A VLSI Chip for the Abnormal Heart Beat Detection Using Convolutional Neural Network,” Sensors, 22(3), 796, 2022. (SCI)

  8. Yuan-Ho Chen* and Hsin-Tung Hua, “VLSI Implementation of Premature Ventricular Complex Abnormal Heartbeat Detection Using a Convolutional Neural Network,” J. Circuits Syst. Comput., Vol. 31, No. 05, 2250087, 2022. (SCI) 

  9. Chung-Yi Li, Yuan-Ho Chen*, Lu-An Lai, Wen-Chi Yeh, and Jun Yang, “Simple and Hardware-efficient Row-based Direct-Mapping Estimators in Fixed-width Modified Booth Multipliers,” International Journal of Circuit Theory and Applications, vol 49, Issue4, pp. 909-920, Apr. 2021. (SCI) 

  10. Yuan-Ho Chen* and Chieh-Yang Liou, “A Low-cost High Efficiency Video Coding Transform Core Using Resource and Time Sharing Architecture,” EURASIP J. Adv. Signal Process., 48, 1-9, Nov. 2020. (SCI) 

  11. Yuan-Ho Chen*, “Improvement of Accuracy of Fixed-Width Booth Multipliers Using Data Scaling Technology,” IEEE Trans. Circuits Syst. II,  vol. 68, pp. 1018-1022, Mar. 2021. (SCI) 

  12. Yuan-Ho Chen* and Shun-Ping Wang, “Low-Cost Implementation of Independent Component Analysis for Biomedical Signal Separation Using Very-Large-Scale Integration” IEEE Trans. Circuits Syst. II,  vol. 67, pp. 3437-3441, Dec. 2020. (SCI)

  13. Yuan-Ho Chen*, “Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme,” Electronics, 9(4), 607, 2020.  (SCI)  

  14. Yuan-Ho Chen, Szi-Wen Chen*, and Min-Xian Wei, “A VLSI Implementation of Independent Component Analysis (ICA) for Biomedical Signal Separation Using CORDIC Engine,” IEEE Trans. Biomed. Circuits Syst., vol. 14, pp. 373-381, Apr. 2020.  (SCI) 

  15. Yuan-Ho Chen* and Yen Juan, “Very-large-scale integration implementation of a convolutional neural network accelerator for abnormal heartbeat detection,” Electron. Lett., vol. 56, issues 7, pp. 330-331, Mar. 2020. (SCI) 

  16. Yun-Hua Tseng and Yuan-Ho Chen*, “Cost-Effective Multi-Standard Video Transform Core Using Time-Sharing Architecture,” EURASIP J. Adv. Signal Process., 49, 1-9, Oct., 2019. (SCI) 

  17. Song-Nien Tang* and Yuan-Ho Chen*, “Area-Efficient FFT Kernel with Improved Use of GI for Multistandard MIMO-OFDM Applications,” Applied Sciences, 9(14), 2877, 2019. (SCI) 

  18. Yuan-Ho Chen*, Yun-Hua Tseng, Pao-Hsien Chu, Yen Juan, Shun-Ping Wang, “VLSI implementation of a cost-efficient 3-lead lossless ECG compressor and decompressor,” Circuits Syst. Signal Process., 39(3), pp. 1665-1671, 2020.  (SCI) 

  19. Yuan-Ho Chen*, “Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array–Based Time-to-Digital Converters with Real-Time Calibration,” Applied Sciences. 9(1), 20, 2019. (SCI) 

  20. Yuan-Ho Chen*, “Run-Time Calibration Scheme for the Implementation of a Robust Field-Programmable-Gate-Array-Based Time-to-Digital Converter,” International Journal of Circuit Theory and Applications, vol. 47, issue 1, pp. 19-31, Jan. 2019. (SCI, top 10% most downloaded papers) 

  21. Yun-Hua Tseng, Yuan-Ho Chen* and Chih-Wen Lu*, “Multiple Leads With a Switch Mode for Lossless and Lossy Compression by Using Very Large Scale Integration Technology,” IEEE Access, vol. 6, pp. 67291-67300, Nov. 2018.  (SCI) 

  22. Yuan-Ho Chen, Szi-Wen Chen*, and Yu Juan, “Very-Large-Scale Integration Implementation of the Integral Pulse Frequency Modulation Model for Spectral Estimation of Heart Rate Variability,” Electron. Lett., vol. 54, issue 23, pp. 1313-1314, Nov. 2018. (SCI)

  23. Yuan-Ho Chen, Chung-Yi Li* and Lu-An Lai, “Fine-tuning accuracy using conditional probability of the bottom sign-bit in Fixed-width Modified Booth Multiplier,” Circuits Syst. Signal Process., vol. 37, issue 7, pp. 3115-3130, July. 2018.  (SCI)

  24. Yun-Hua Tseng, Yuan-Ho Chen* and Chih-Wen Lu*, “Adaptive Integration of the Compressed Algorithm of CS and NPC for the ECG Signal Compressed Algorithm in VLSI Implementation,” Sensors. vol. 17, pp. 2288, Oct. 2017. (SCI)

  25. Yuan-Ho Chen* and Yi-Fan Ko, “High-throughput IDCT architecture for high-efficiency video coding (HEVC),” International Journal of Circuit Theory and Applications, vol. 45, issue 12, pp. 2260-2269, Dec. 2017. (SCI)

  26. Yuan-Ho Chen*, “A counting-weighted calibration method for a field-programmable-gate-array-based time-to-digital converter,” Nuclear Instruments and Methods in Physics Research Section A., vol. 854, pp. 61-63, May 2017. (SCI)

  27. Yuan-Ho Chen* and Yun-Hua Tseng, “Low-cost Multi-standard Video Transform Core Using Time-distribution Scheme,” Electron. Lett., vol. 52, issue 24, pp. 1980-1982, Nov. 2016. (SCI)

  28. Yun-Hua Tseng, Yuan-Ho Chen*, Tze-Yang Kao, and Chih-Wen Lu, “Low-cost Multi-Standard Simultaneous Forward and Inverse Video Transform Core,” International Journal of Circuit Theory and Applications, vol. 44, issue 8, pp. 1572-1588, Aug. 2016. (SCI)

  29. Wen-Quan He, Yuan-Ho Chen*, and Shyh-Jye Jou, “Dynamic Error-compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series,” Circuits Syst. Signal Process, vol. 35, no. 8, pp. 2972-2991, Aug. 2016. (SCI)

  30. Ping-Yeh Yin, Chih-Wen Lu*, Yuan-Ho Chen, Hsin-Chin Liang, and Sheng-Pin Tseng “A 10-Bit Low-Power High-Color-Depth Column Driver with Two-Stage Multi-Channel RDACs for Small-Format TFT-LCD Driver ICs,” IEEE Journal of Display Technology, vol. 11, no. 12, pp. 1061-1068, Dec. 2015. (SCI)

  31. Szi-Wen Chen* and Yuan-Ho Chen, “Hardware Design and Implementation of a Wavelet De-noising Procedure for Medical Signal Preprocessing,” Sensors, vol 15, pp. 26396-26414, 2015. (SCI)

  32. Yuan-Ho Chen*, “Area-Efficient Fixed-Width Squarer with Dynamic Error-Compensation Circuit,” IEEE Trans. Circuits Syst. II., vol. 62, no. 9, pp. 851-855, Sep. 2015. (SCI)

  33. Wen-Quan He, Yuan-Ho Chen*, and Shyh-Jye Jou, “High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation,” IEEE Trans. Circuits Syst. I. , vol. 62, no. 8, pp. 2052-2061, Aug. 2015. (SCI)

  34. Yuan-Ho Chen* and Chieh-Yang Liu, “Area-efficient Video Transform for HEVC Applications,” Electron. Lett., vol. 51, no. 14, pp. 1065-1067, Jul, 2015. (SCI)

  35. Yuan-Ho Chen*, “An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 1, pp. 203-207, Jan. 2015. (SCI)

  36. Yuan-Ho Chen*, Ruei-Yuan Jou, Tsin-Yuan Chang, and Chih-Wen Lu, “A High-Throughput and Area-Efficient Video Transform Core with a Time Division Strategy,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 11, pp. 2268-2277, Nov. 2014. (SCI)

  37. Yuan-Ho Chen* and Hsiao-Tzu Liu, “Hardware-Efficient Multi-Standard Video Transform Core,” J. Circuits Syst. Comput., vol. 23, no 8, 1450119, 2014. (SCI)

  38. Yuan-Ho Chen*, “Low-cost fixed-width squarer by using a probability-compensated circuit,” Electron. Lett., vol. 50, no. 11, pp. 795-797, May 2014. (SCI)

  39. Yuan-Ho Chen*, Chih-Wen Lu, Shian-Shing Shyu, Chung-Lin Lee, and Ting-Chia Ou, “A Multi-stage Fault-tolerant Multiplier with Triple Module Redundancy (TMR) Technique,” J. Circuits Syst. Comput., vol. 23, issue 5, 1450074, May 2014. (SCI)

  40. Wen-Quan He, Yong-Ming Chang, and Yuan-Ho Chen*, “High-Throughput Rate FFT VLSI Implementation on Linear Array Based Design,” Journal of Advanced Engineering, vol. 9, no 2, pp. 87-92, Apr. 2014.

  41. Yuan-Ho Chen*, Jyun-Neng Chen, Tsin-Yuan Chang, and Chih-Wen Lu, “A High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 3, pp. 463-474, Mar. 2014. (SCI)

  42. Yuan-Ho Chen* and Tsin-Yuan Chang, “A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 4, pp. 655-664, Apr. 2012. (SCI)

  43. Yuan-Ho Chen* and Tsin-Yuan Chang, “A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers,” IEEE Trans. Circuits Syst. I, vol. 59, no. 3, pp. 594-603, Mar. 2012. (SCI)

  44. Chung-Yi Li*, Yuan-Ho Chen, Tsin-Yuan Chang, Lih-Yuan Deng, and Kiwing To, “Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 2, pp. 385-389, Feb. 2012. (SCI)

  45. Yuan-Ho Chen*, Tsin-Yuan Chang, and Chung-Yi Li, “Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias,” IEEE J. Emerging Sel. Topics Circuits Syst., vol. 1, no. 3, pp. 277-288, Sep. 2011. (SCI)

  46. Chung-Yi Li*, Yuan-Ho Chen, Tsin-Yuan Chang, and Jyun-Neng Chen, “A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications,” IEEE Trans. Circuits Syst. II, vol. 58, no. 4, pp. 215-219, Apr. 2011. (SCI)

  47. Yuan-Ho Chen*, Tsin-Yuan Chang, and Chung-Yi Li, “High Throughput DA-based DCT with High Accuracy Error-Compensated Adder Tree,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 4, pp. 709-714, Apr. 2011. (SCI)

  48. Bor-Sen Chen*, Bore-Kuen Lee, and Yuan-Ho Chen, “Power Control for CDMA Cellular Radio Systems via L1 Optimal Predictor,” IEEE Trans. Wireless Commun., vol. 5, no. 11, pp. 2914-2922, Oct. 2006. (SCI)

  49. Bore-Kuen Lee, Yuan-Ho Chen, and Bor-Sen Chen*, “Robust H_inf Power Control for CDMA Cellular Communication Systems,” IEEE Trans. Signal Processing, vol. 54, no. 10, pp. 3947-3956, Oct. 2006. (SCI)

Conference Papers:

• 1. Yuan-Ho Chen, Szi-Wen Chen, Yen Juan, Rou-Shayn Chen, “A Compact and Energy-Efficient Heart Rate Variability (HRV) Spectral Analysis Chip for Wearable Healthcare Devices” in Proc. 47th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC),  Copenhagen/Denmark, July 14-17, 2025.

  2. Szu-Wei Chien and Yuan-Ho Chen, “Simulated Annealing Hardware Architecture for Max-Cut Combinatorial Optimization” in Proc. IEEE GCCE, Kokura/Japan, Oct. 29 – Nov. 1, 2024.

  3. Wu-Hsun Chu and Yuan-Ho Chen, “A Simplified Simulated Annealing Algorithm and Its Implementation” in Proc. IEEE GCCE, Kokura/Japan, Oct. 29 – Nov. 1, 2024.

  4. Wei-Chen Lin and Yuan-Ho Chen, “Low-error Fixed-width Booth Multiplier with High-radix Booth Encoder” in Proc. ISOCC, Sapporo/Japan, Aug. 19-22, 2024.

  5. Kai-Fen Chang and Yuan-Ho Chen, “VLSI Implementation of Enhanced Image Classification using Recursive Convolutional Neural Networks” in Proc. ISASD, Tokyo/Japan, July, 8-11, 2024.

  6. Yu-Chen Wu, Chia-Chi Lin, Pei-Hao Kuo, Yuan-Ho Chen, and Nai-Chuan Chen “Efficient VLSI Chip for PVC Detection Through Ternary Quantization Neural Networks” in Proc. IEEE ICASI, Kyoto/Japan, Apr. 17-21, 2024.

  7. Kai-Lun Lin, Pei-Hao Kuo, Chia-Chi Lin, Yuan-Ho Chen, and Yi-Chyun Chiang “Efficient VLSI Realization of Tiny-YOLOv2 for High-Speed Object Detection” in Proc. IEEE ICASI, Kyoto/Japan, Apr. 17-21, 2024.

  8. Yun-Ting Zhang, Chin-Fu Nien, Chia-Wei Lin, Wen-Jui Chao, Chen-Yu Liu, Lien-Po Yu, and Yuan-Ho Chen, “An Automated Toolchain for QUBO-based Optimization with Quantum inspired Annealers” in Proc. ISOCC, Jeju/Korea, Oct. 25-28, 2023.

  9. Song-Nien Tang, Yuan-Ho Chen, Yu-Wei Chang, Yu-Ting Chen, and Shuo-Hung Chou, “Hybrid CNN-LSTM Network for ECG Classification and Its Software-Hardware Co-Design Approach” in Proc. ISOCC, Jeju/Korea, Oct. 25-28, 2023.

  10. Hsin-Tung Hua and Yuan-Ho Chen, “VLSI Implementation of the Annealing Processor Chips for Traveling Salesman Problem” in Proc. IEEE ICKII, Sapporo/Japan, August 11-13, 2023.

  11. Yuan-Ho Chen, “Implementation of the FPGA-based multi-channel TDC with Auto Calibration Technology” in Proc. IEEE ICASI, Tokyo/Japan, April 21-25, 2023.

  12. Kai-Fen Chang, and Yuan-Ho Chen, “High Accuracy Abnormal ECG Detection Chip Using a Simple Neural Network” in Proc. ISOCC, Gangwon-do/Korea, Oct. 19-22, 2022.

  13. Yi-Fan Chen, Wei-Jhong Huang, Yi-Wei Zeng, Hsin-Tung Hua, Kai-Fen Chang, and Yuan-Ho Chen, “Very-large-scale Integration of a Dual-lead Electrocardiogram Compression Chip with Modified Huffman Encoding” in Proc. IEEE LifeTech, Osaka/Japan, Mar. 7-9, 2022. 

  14. Yu-Lun Huang, Pei-Jung Chang, and Yuan-Ho Chen, “A Premature Ventricular Complex Detection Chip Using Convolution Neural Network,” in Proc. IEEE ICAIIC, Fukuoka/Japan, 2020. 

  15. Yuan-Ho Chen*, “Dual-mode FPGA-based Triple-TDC with Real-time Calibration and Triple Modular Redundancy (TMR) Scheme,” in Proc. IEEE ICASI, Fukuoka/Japan, 2019. 

  16. Yuan-Ho Chen*, “A Real-time Calibration Architecture with Dual Delay Line for the Implementation of FPGA-based TDC,” in Proc. IEEE ICASI, Tokyo/Japan, 2018. 

  17. Yuan-Ho Chen, Ming-Han Tsai, and Chih-Wen Lu*, “QRS Complex Detection Based On Wavelet Decomposition,” in Proc. IEEE ICASI, Sapporo/Japan, 2017.

  18. Min-Xian Wei, Yu Juan, and Yuan-Ho Chen, “A VLSI implementation of Independent Component Analysis (ICA) for Biomedical Signal Separation,” in Proc. IEEE ICASI, Sapporo/Japan, 2017.

  19. Yu Juan, Min-Xian Wei, and Yuan-Ho Chen, “VLSI Implementation of the Integral Pulse Frequency Modulation Model for Heart Rate Variability System,” in Proc. IEEE ICASI, Sapporo/Japan, 2017.

  20. Yuan-Ho Chen*, “A 50-ps FPGA-based TDC for Digital PET Applications,” in Proc. ACENS, Sapporo/Japan, 2017.

  21. Yun-Hua Tseng, Yuan-Ho Chen*, and Chih-Wen Lu, “Cost-Effective Multi-standard Video Transform Core Using Time-distribution Scheme,” in Proc. IEEE ICCP, Taipei/Taiwan, 2016.

  22. Yun-Hua Tseng, Yuan-Ho Chen*, and Chih-Wen Lu, "Cost-Effective Multi-Standard Video Transform Core Using Time-Sharing Architecture," in Proc. IEEE ISNE, Hsinchu/Taiwan, 2016.

  23. Yuan-Ho Chen*, “A High Resolution FPGA-based Weighted Delay Line TDC with Nonlinearity Calibration,” in Proc. ACENS, Fukuoka/Japan, 2016, pp. 713-720.

  24. Yi-Fan Ko, Chieh-Yang Liua, and Yuan-Ho Chen*, “A High Throughput Video Transform Architecture for High Efficiency Video Coding (HEVC) Applications,” in Proc. APCEAS, Osaks/Japan, 2015, pp. 450-455.

  25. Chieh-Yang Liu, Wen-Quan He, Yung-Ming Chang, and Yuan-Ho Chen*, “Low-Cost Video Transform for HEVC,” in Proc. IEEE ICIST, Shenzhen/China, 2014, pp. 221-224. (EI) 

  26. Wen-Quan He, Chieh-Yang Liu, Wei-Yi Liu, and Yuan-Ho Chen*, “A High Accuracy Fixed-width Booth Multiplier Using Select Probability Estimation Bias,” in Proc. IEEE ICIST, Shenzhen/China, 2014, pp. 385-388. (EI)

  27. Yuan-Ho Chen*, “A High Resolution FPGA-based Merged Delay Line TDC with Nonlinearity Calibration,” in Proc. IEEE ISCAS, Beijing/China, 2013, pp. 2432-2435. (EI)

  28. Ping-Yeh Yin, Yuan-Ho Chen, Chih-Wen Lu*, Shian-Shing Shyu, Chung-Lin Lee, Ting-Chia Ou, and Yo-Sheng Lin, “A Multi-Stage Fault-Tolerant Multiplier with Triple Module Redundancy (TMR) Technique,” in Proc. IEEE ISMS, Bangkok /Thailand, 2013, pp. 636-641. (EI)

  29. Jian-Shou Chen, Chih-Wen Lu*, Chin Hsia, and Yuan-Ho Chen, “A Low Noise Amplifier Employing Noise Canceling Technique for Ultrasound System Applications,” in Proc. IEEE IMSNA, Shenyang/China, 2012, pp. 35-38. (EI)

  30. Yuan-Ho Chen, Chih-Wen Lu*, Tsin-Yuan Chang, and Chin Hsia, “A High Resolution FPGA-Based TDC with Nonlinearity Calibration,” in Proc. IEEE IMSNA, Shenyang/China, 2012, pp. 44-47. (EI)

  31. Yuan-Ho Chen, Chih-Wen Lu*, Hsin-Chen Chiang, Tsin-Yuan Chang, and Chin Hsia, “A Low-Error Statistical Fixed-Width Multiplier and Its Applications,” in Proc. IEEE IMSNA, Shenyang/China, 2012, pp. 39-43. (EI)  

  32. Yuan-Ho Chen, Hsin-Chen Chiang, Tsin-Yuan Chang, Chih-Wen Lu*, and Pei-Yi Lai Li, “High Accuracy Fixed-width Booth Multipliers with Probabilistic Estimation Compensated Method,” in Proc. IEEE ICETEC, Three Gorges/China, 2012, pp. 1460-1463. (EI)  

  33. Yuan-Ho Chen*, Tsin-Yuan Chang, and Chih-Wen Lu, “A Low-Cost and High-Throughput Architecture for H.264/AVC Integer Transform by Using Four Computation Streams,” in Proc. IEEE ISIC, Singapore, 2011, pp. 380-383. (EI)  

  34. Yuan-Ho Chen*, Tsin-Yuan Chang, and Ruei-Yuan Jou, “A Statistical Error-Compensated Booth Multiplier and Its DCT Applications,” in Proc. IEEE Region 10 Conf. (TENCON), Fukuoka/Japan, 2010, pp. 1146-1149. (EI)

Domestic Conference Papers:

• 1. Pei-Hao Kuo, Yuan-Ho Chen, and Yi-Chyun Chiang, “Efficient VLSI Implementation of Gradient Domain Tone Mapping for Image Enhancement” in Proc. VLSI Design/CAD Symposium, Taiwan, 2024.

  2. Yu-Jie Yen and Yuan-Ho Chen, “Implementation of an Annealing Chip for Advanced Quantum Computing Applications” in Proc. VLSI Design/CAD Symposium, Taiwan, 2023.

  3. Kai-Lun Lin and Yuan-Ho Chen, “A VLSI Implementation of the Tiny-YOLOv2 Algorithm,” in Proc. VLSI Design/CAD Symposium, Taiwan, 2023.

  4. Pei-Jung Chang, Hsin-Tung Hua, and Yuan-Ho Chen, “VLSI Implementation of the Abnormal Heart Beat Detector using CNN Accelerator,” in Proc. VLSI Design/CAD Symposium, online, Taiwan, 2021.

  5. Hong-Wen Jian, Hsin-Tung Hua, and Yuan-Ho Chen, “Accuracy Improvement of the Abnormal ECG Detection Chip,” in Proc. VLSI Design/CAD Symposium, online, Taiwan, 2021.

  6. Yu-Chen Wu and Yuan-Ho Chen, “Cost-efficiency VLSI Chip for PVC Detection Using the Ternary Quantization Neural Networks,” in Proc. VLSI Design/CAD Symposium, Taichung, Taiwan, August 4-7, 2020. 

  7. Hsin-Tung Hua and Yuan-Ho Chen, “VLSI Implementation of Premature Ventricular Complex Detection,” in Proc. VLSI Design/CAD Symposium, Taichung, Taiwan, August 4-7, 2020. 

  8. Yen Juan, Shung-Ping Wang, and Yuan-Ho Chen, “VLSI Implementation of the Integral Pulse Frequency Modulation Model for Heart Rate Variability System,” in Proc. VLSI Design/CAD Symposium, Taiwan, August 6-9, 2019.

  9. Shung-Ping Wang, Yen Juan, and Yuan-Ho Chen, “A VLSI Implementation of Low Cost Independent Component Analysis (ICA) for Biomedical Signal Separation,” in Proc. VLSI Design/CAD Symposium, Taiwan, August 6-9, 2019. 

  10. Yuan-Ho Chen, Chung-Yi Li, and Lu-An Lai, “Fine-tuning accuracy using conditional probability of bottom sign-bit in Fixed-width Modified Booth Multiplier,” in Proc. VLSI Design/CAD Symposium, Taiwan, August 1-4, 2017.

  11. Yun-Hua Tseng, Yuan-Ho Chen, and Chih-Wen Lu, “Adaptive Integrating Compressed Algorithm of CS and NPC for ECG Signal Compressed Algorithm,” in Proc. VLSI Design/CAD Symposium, Taiwan, August 1-4, 2017.

  12. Min-Xian Wei, Yu Juan, Bing Jhe Chi, and Yuan-Ho Chen*, “VLSI implementation of Independent Component Analysis (ICA) for Biomedical Signal Separation,” in Proc. VLSI Design/CAD Symposium, Taiwan, August 1-4, 2017.

  13. Wei-Ching Hsiao, Hsin-Han Chu, Chieh-Yang Liu, and Yuan-Ho Chen*, “Design of Automotive Electronics Based on FPGA” in Proc. Intelligent Automotive Electronics Workshop, Taoyuan, Dec. 2, 2014.

  14. Wei-Yi Liu, Wen-Quan He, and Yuan-Ho Chen*, “High-accuracy and Area-efficiency Fixed-width Booth Multiplier” in Proc. Intelligent Automotive Electronics Workshop, Taoyuan, Dec. 2, 2014.

  15. Chieh-Yang Liu, Yi-Fan Ko, and Yuan-Ho Chen*, “Low-cost Video Transform for High Efficiency Video Coding (HEVC) Applications,” in Proc. VLSI Design/CAD Symposium, Taichung, Taiwan, August 5-8, 2014.

  16. Yong-Ming Chang, Wen-Quan He, and Yuan-Ho Chen*, “A Low-Cost FFT Processor for DVB-T Application” in Proc. Intelligent Automotive Electronics Workshop, Taoyuan, Dec. 10, 2013.

  17. Wen-Ch’uan Ho, Yong-Ming Chang, and Yuan-Ho Chen*, “High-Throughput VLSI FFT Architecture With Systolic Array,” in Proc. 2013 VLSI Design/CAD Symposium, Kaohsiung, August 6-9, 2013.

  18. Yuan-Ho Chen* and Tsin-Yuan Chang, “A Low-cost Architecture for High-throughput Multi-path Transform in Video Compression Applications,” in Proc. VLSI Design/CAD Symposium, Yunlin, August 2-5, 2011, pp. 25-28.

  19. Ruei-Yuan Jou, Yuan-Ho Chen*, Tze-Yang Kao, and Tsin-Yuan Chang, “A High Performance Video Transform Engine by Using Simultaneous Forward and Inverse DCT,” in Proc. VLSI Design/CAD Symposium, Yunlin, Taiwan, August 2-5, 2011, pp. 572-575.

  20. Hsin-Chen Chiang, Yuan-Ho Chen*, and Tsin-Yuan Chang, “Low-Error Fixed-Width Two’s-Complement Multipliers with Statistical Compensation Circuit,” in Proc. VLSI Design/CAD Symposium, Yunlin, Taiwan, August 2-5, 2011, pp. 29-32.

  21. Yuan-Ho Chen* and Tsin-Yuan Chang, “High Performance DA-Based DCT with High Accuracy Error Compensated Adder Tree,” in Proc. VLSI Design/CAD Symposium, Hualien, Taiwan, August 4-7, 2009.