COMPUTER ORGANIZATION AND ARCHITECTURE
22CS201 COMPUTER ORGANIZATION AND ARCHITECTURE
Course Objective:
1. To study the concepts of the basic structure and operation of a digital computer
2. To learn the working of various of arithmetic operations
3. To understand the different types of control and the concept of pipelining
4. To comprehend the significance of memory organization
5. To understand the different types of communication with I/O devices and standard I/O interfaces.
Course Outcomes: Upon completion of the course, students shall have ability to
CO 1 Understand the computer architecture and its instructions sets, addressing modes. [U]
CO 2 Design and Develop different types of arithmetic circuits in a computer. [AP]
CO 3 Assess the performance of CPU by applying various design techniques and design a simple CPU using pipeline structures. [AP]
CO 4 Understand the different types of input, output device and their interfaces. [U]
CO 5 Design a flowchart for memory access and Parallel Processing. [AP]
CO 6 Build a memory module and access its operation by interfacing with the CPU. [AP]
Course Contents:
MODULE I Functional Blocks of a Computer and Data Representation 15 Hours
Functional Blocks of a Computer: Functional blocks and its operations. Instruction set architecture of a CPU - registers, instruction execution cycle, Data path, RTL interpretation of instructions, instruction set. Performance metrics. Addressing modes. Data Representation: Signed number representation, fixed and floating point representations, character representation. Computer arithmetic - integer addition and subtraction, ripple carry adder, carry look-ahead adder, etc. multiplication - shift-and add, Booth multiplier, carry save multiplier, etc. Division restoring and non-restoring techniques, floating point arithmetic.
MODULE II Control unit, I/O systems and Pipelining 15 Hours
CPU control unit design: Hardwired and micro-programmed design approaches, Peripheral devices and their characteristics: Input-output subsystems, I/O device interface, I/O transfers program controlled, interrupt driven and DMA, privileged and non-privileged instructions, software interrupts and exceptions. Programs and processes-role of interrupts in process state transitions, I/O device interfaces - SCII, USB. Basic concepts of pipelining, throughput and speedup, pipeline hazards.
MODULE III Parallel Processors and Memory Organization 15 Hours
Parallel Processors: Introduction to parallel processors, Concurrent access to memory and cache coherency. Introduction to multicore architecture. Memory system design: semiconductor memory technologies, memory organization. Memory interleaving, concept of hierarchical memory organization, cache memory, cache size vs. block size, mapping functions, replacement algorithms, write policies.
Case Study: Instruction sets of some common CPUs - Design of a simple hypothetical CPU- A sequential Y86-64 design-Sun Ultra SPARC II pipeline structure
Total Hours: 45 Hours
Text Books:
1. David A. Patterson and John L. Hennessy, “Computer Organization and Design: The Hardware/Software Interface”, 6th Edition, Morgan Kaufmann/Elsevier, 2020.
2. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian, “Computer Organization and Embedded Systems”, McGraw- Hill, 6th Edition 2017.
Reference Books:
1. John P. Hayes, “Computer Architecture and Organization”, McGraw-Hill, 3rd Edition, 2017
2. William Stallings, “Computer Organization and Architecture Designing for Performance”, 11th Edition, Pearson Education 2018.
3. Vincent P. Heuring and Harry F. Jordan, “Computer System Design and Architecture”, 2nd Edition, Pearson Education 2004.
Web References:
1. https://www.geeksforgeeks.org/computer-organization-and-architecture-tutorials/
