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The purpose of this page to modify the "wikipedia" equation to be correct for stacked, saturated nFETs in subthreshold operation.  The equation is then verified with test data from a 350nm nFET device.

Wikipedia's description of MOSFET operation in subthreshold is inaccurate.  A few times I tried to update Wikipedia for the correct subthreshold equations, but someone always thought to change it back.  I could always tell when a student used wikipedia instead of the class notes because the values were always off.  This is particularly true for subthreshold behavior.   

Devices in the subthreshold regime have simple physics and the operation is well understood, but this operation is inaccurately described in reference texts when the source terminal is not tied to the bulk[1].  This inaccuracy exists from the Grey and Meyer text, which is otherwise quite good, to Internet references, such as[2], and this inaccuracy exists because the model is too simple.  The simplifications do not hold in submircon processes, and have never been correct unless you were modeling a single gate with the source tied to bulk. Consider the stacked devices in Figure 1, M2 does not have the source tied to the bulk voltage, whereas M1 does.  This discrepancy is the root cause of error.

nFET layout

Figure 1: The illustration represents the drawn nFET layout, terminal voltages, and the effect of these voltages on the surface potential, ψs. Assuming that both Cox and Cdep are fixed, the coupling from the gate voltage to the surface potential can be described as ψs = κVg. This also shows the falsity of a VGS term in subthreshold because the gate coupling is independent of the source voltage. For example, in the illustration, the source of M2 is not necessarily at the same potential as the bulk. 

The common approximation for subthreshold operation of the nFET for a device in saturation is 

Grey and Meyer subvt equation

where IDo is the current at threshold, UT is the thermal voltage and η is the “subthreshold slope factor.” This slope factor is defined as 

eta as depletion

where Cox is the oxide capacitance per unit area, and Cdep is the depletion capacitance per unit area. The Cox capacitor is a physical capacitor and effectively does not change; whereas, the Cdep capacitance changes as the channel inverts. The divider in (2) is correct; however, as it applies to (1) is not true to the physics [3, 4]. Consider the illustration of the nFET channel in Figure 11. The current flow in subthreshold is dominated by diffusion movement, and the barrier is completely dependent on the surface potential, ψs. The surface potential is then the related to the gate voltage, Vgb, as referenced from the bulk by 

where κ is the capacitive divider to the channel surface through the gate oxide defined as

 This term is equivalent to the η in (2); however, what one should notice is that the zeroth order analysis of this divider is independent of the source voltage, Vs. Rewriting (1) to reflect this, the resulting current approximation is 

which gives a channel divider that is independent of the source voltage.  The slope of the subthreshold region becomes κ/UT.  Of course, the current approximation will change slightly due to DIBL effects, mobility degradation, and the encroachment of the depletion regions [4,5,6,7]; however, (5) is a better approximation than what is given in (1).  The Cdep capacitance changes as the channel inverts; however, the κ description of the divider to the surface holds well until one approaches threshold [8].  

The difference in current between (1) and (5) can clearly be seen in Figure 2.  (5) correctly approximates the device behavior when the source is not attached to the bulk, which is denoted by the green, dashed line.  (1) is show as the red, dashed line that incorrectly models the behavior of the measured device, which is the solid blue line.

Figure 2: A current measurement shows the effect of using the VGS instead of κVgb for the model when VS = 100mV with a bulk reference of zero volts. 

  1. [1]  Gray, P., Hurst, P., Meyer, R., and Lewis, S., Analysis and design of analog integrated circuits. Wiley, 2001. 

    [2], 7 SEP 2013.

    [3]  Grove, A., Physics and technology of semiconductor devices. Wiley New York, 1967. 

    [4]  Mead, C. and Analog, V., Neural Systems. Addison-Wesley, 1989. 

    [5]  Fjeldly, T. and Shur, M., “Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs,” IEEE Transactions on Electron Devices, vol. 40, no. 1, pp. 137–145, 1993. 

    [6]  van Langevelde, R. and Klaassen, F., “Effect of gate-field dependent mobility degradation on distortion analysis in MOSFETs,” Electron Devices, IEEE Transactions on, vol. 44, no. 11, pp. 2044–2052, 1997. 

    [7]  Watt, J. and Plummer, J., “Universal Mobility-Field Curves for Electrons and Holes in MOS Inversion Layers,” in VLSI Technology, 1987. Digest of Technical Papers. Symposium on, pp. 81–82, 1987. 

    [8]  Odame, K., McDonald, E., and Minch, B., “Highly linear, wide-dynamic- range multiple-input translinear element networks,” in Signals, Systems and Computers, 2003. Conference Record of the Thirty-Seventh Asilomar Conference on, vol. 2, 2003.