.align n
Align the next datum on a 2^n byte boundary. For example, .align 2 aligns the next value on a word boundary. .align 0 turns off automatic alignment of .half, .word, .float, and .double directives until the next .data or .kdata directive.
.ascii str
Store the string in memory, but do not null-terminate it.
.asciiz str
Store the string in memory and null-terminate it.
.byte b1, ..., bn
Store the n values in successive bytes of memory.
.data
The following data items should be stored in the data segment. If the optional argument addr is present, the items are stored beginning at address addr.
.double d1, ..., dn
Store the n floating point double precision numbers in successive memory locations.
.extern sym size
Declare that the datum stored at sym is size bytes large and is a global symbol. This directive enables the assembler to store the datum in a portion of the data segment that is efficiently accessed via register $gp.
.float f1, ..., fn
Store the n floating point single precision numbers in successive memory locations.
.globl sym
Declare that symbol sym is global and can be referenced from other files.
.half h1, ..., hn
Store the n 16-bit quantities in successive memory halfwords.
.kdata
The following data items should be stored in the kernel data segment. If the optional argument addr is present, the items are stored beginning at address addr.
.ktext
The next items are put in the kernel text segment. In SPIM, these items may only be instructions or words (see the .word directive below). If the optional argument addr is present, the items are stored beginning at address addr.
.space n
Allocate n bytes of space in the current segment (which must be the data segment in SPIM).
.text
The next items are put in the user text segment. In SPIM, these items may only be instructions or words (see the .word directive below). If the optional argument addr is present, the items are stored beginning at address addr.
.word w1, ..., wn
Store the n 32-bit quantities in successive memory words.
In all instructions below, Src2 can either be a register or an immediate value (a 16 bit integer). The immediate forms of the instructions are only included for reference. The assembler will translate the more general form of an instruction (e.g., add) into the immediate form (e.g., addi) if the second argument is constant.
In all instructions below, Src2 can either be a register or an immediate value (a 16 bit integer).
In all instructions below, Src2 can either be a register or an immediate value (integer). Branch instructions use a signed 16-bit offset field; hence they can jump 2^15-1 instructions (not bytes) forward or 2^15 instructions backwards. The jump instruction contains a 26 bit address field.
The MIPS has a floating point coprocessor (numbered 1) that operates on single precision (32-bit) and double precision (64-bit) floating point numbers. This coprocessor has its own registers, which are numbered f0-f31. Because these registers are only 32-bits wide, two of them are required to hold doubles. To simplify matters, floating point operations only use even-numbered registers - including instructions that operate on single floats. Values are moved in or out of these registers a word (32-bits) at a time by lwc1, swc1, mtc1, and mfc1 instructions described above or by the l.s, l.d, s.s, and s.d pseudoinstructions described below. The flag set by floating point comparison operations is read by the CPU with its bc1t and bc1f instructions. In all instructions below, FRdest, FRsrc1, FRsrc2, and FRsrc are floating point registers (e.g., f2).