Snapshot Tutorial

Requirements: This tutorial assumes that you have a Xilinx/MATLAB/CASPER setup for ROACH model compilation and you've already done Tutorial 1 from CASPER.

Introduction

Snapshot is very a useful block from the CASPER library which is primary used for extracting raw data from the ADC to the computer. This data (which is also refer as 'snapshot') can be plotted to debug a problem with the ADCs, and is also used to calibrate ADCs that use multi-core sampling schemes, synchronize multiple ADCs, among other things.

In this tutorial we'll build a very rudimentary oscilloscope to test the capabilities of the snapshot block.

Building the Model

Add a Xilinx 'System Generator' block and a 'XSG_core_config block' as per Tutorial 1. Select the ROACH board you are using in the 'XSG_core_config' block parameters, for this tutorial we'll use ROACH1. Also change the 'User IP Clock Source' to 'adc0_clk'. This means that the ROACH board will use the clock provided by the ADC located the ZDOK0 interface. Let's change the 'User IP Clock Rate (MHz)' to 125.

Add the corresponding ADC from your ROACH board, in this case ADC083000x2. Edit the block parameters by unchecking the 'Use ZDOK1' (as we'll be using only the ADC in ZDOK0), and the 'ADC Clock Rate' to 500MHz.

Note: In ROACH1 with ADC083000x2 the ADC clock should be = 4 x User IP (FPGA) Clock Rate. However if these values don't match the compiling tools will simply use the clock rate of the ADC. For ROACH2 the relation is: ADC Clock = 8 x FPGA Clock.

The snapshot block can receive only one input at a time, so we should create a bus of all the data we are receiving. This can be done with the 'create_bus' block, as shown here:

Finally we add the Snapshot block. For this simple tutorial we don't need all the advanced options from the block so you can uncheck all the boxes. Also be sure to use bram as 'Data Storage' and that the 'Data Width' match your input data width. Again we won't be using advance triggering options so you can fix the 'we' and 'trig' of the block to 1 with a boolean constant block.

That's it for the model. Compile it and load it to ROACH with one of the methods described here.

Snapshot Script

Once the model is compiled and uploaded into ROACH is time to see the snapshot. First make sure you ADC clock has the correct frequency. If you are not sure how to do this, check this memo.

Next, prepare a signal generator to test the snapshot. Make sure you have set a power level that doesn't saturate (or damage!) your ADC.

Once all that is done you can use this simple script to extract and plot the data from the ADC, it assumes you have the correct libraries installed from here.

If everything works correctly you should see the generator signal plotted in your computer. Here is an example of a 10MHz sine wave using the snapshot model. You can get the snapshot Simulink and compiled model at the bottom of the page.

ROACH2 Notes

lf you are using ROACH2 for this tutorial you have to be aware of some details:

• ROACH2 uses a different ADC board, namely ASIAA ADC5G (ADC1x5000-8)
• ROACH2 ADC's has different allowed compilation frequencies, as mentioned in this memo. So use a different clock rate for the ADC.
• Normally you want the sampled data type to be signed and centered at zero, while most ADC output the data as unsigned values from zero to the max output. ROACH1 ADC block fix this internally so you don't have to do anything, but for ROACH2 ADC you must convert the data type manually to 2's-complement. This is done by using the 'conv' block from the CASPER DSP Blockset.

A ROACH2 snapshot model should look like this:

You can find the Simulink and compiled models for ROACH2 below.

https://drive.google.com/open?id=0B84PmABXW13RSUFleHZNbS1KVDA