TUBE on FPGA

Like many before us, we've wondered about re-implementing a TUBE, somehow.

(We're not planning to step on the toes of Robert or John or anyone else who sells things. We're mainly aiming to scratch an itch. We intend to release our code as open source, to help others who are perhaps more interested in building things than using them, and in the hope that we can pool our bug fixes, if any.)

What's a TUBE? A TUBE is many things: it's an Acorn invention for the BBC micro, specifically a 40-pin interface from a host processor to a second processor, it's a message-passing protocol with separate streams for read/write, for file operations and for other OS calls, and it's a 40-pin part which implements the buffers and control logic for that protocol. The TUBE demotes an 8bit BBC micro from a standalone computer into a smart peripheral for a second processor, which could be anything from a PDP-11, a slightly faster 6502, a Z80 for all-important CP/M compatibility, up to an ARM eval board.

This post is a good overview, and the Acorn Application Note is good too. There's lot of good info on David's pages.

Our first thoughts were to try to fit the TUBE logic in the CPLD on our Level 1B board so we'd have an instant 65816 second processor. Unfortunately, a genuine TUBE needs too many registers, and even a reduced one looks like it will be hard to fit on our 9572.

A TUBE with reduced buffers, by the way, may be an idea that's arisen more than once, but we're grateful to John for confirming that it's workable (and to Greg for bringing it up in that discussion.)

Our present state of play is a working but non-final verilog, not yet released, which seems to work as a TUBE when implemented in a 40-pin GODIL module from OHO and placed in a Master's internal second processor:

We see this as a means to an end: we can then integrate this TUBE module with other RTL to make a one-module second processor. Our 24-pin GOP module has on-board RAM, so that's the likely target platform. The first processor is likely to be the T65, but there are several possibilities beyond that: FPGA capacity is the main limitation, and 8-bit machines are small compared to these FPGAs.

As for those buffers, Mark counts at least 208 register bits in the original. This is our configuration, subject to change:

Host-> Parasite Parasite->host

Reg1 1 byte 1 byte

Reg2 1 byte 1 byte

Reg3 2 byte 2 byte

Reg4 1 byte 1 byte

We measure a little over 2% performance loss compared to the original (which has a 24 byte FIFO in the p->h direction for Reg1.) Reg3 is special because it handles two-byte transfers more or less as single actions, whereas Reg1 is a more ordinary FIFO.

For an initial and some interim releases of our open-source code, please see the Files page.