Journals
J9: Ayan Palchaudhuri, Digvijay Anand and Anindya Sundar Dhar, “FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion”, Journal of Parallel and Distributed Computing (JPDC) vol. 167, pp. 50-63. (2022)
J8: Ayan Palchaudhuri and Anindya Sundar Dhar, "Speed-Area Optimized VLSI Architecture of Multi-bit Cellular Automaton Cell based Random Number Generator on FPGA with Testable Logic Support", Journal of Parallel and Distributed Computing (JPDC), vol. 151, pp. 13-23. (2021)
J7: Ayan Palchaudhuri, Sandeep Sharma and Anindya Sundar Dhar, "Design Automation for Tree based Nearest Neighborhood Aware Placement of High Speed Cellular Automata on FPGA with Scan Path Insertion", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 26, no. 4, pp. 31:1-31:34. (2021)
J6: Ayan Palchaudhuri and Anindya Sundar Dhar, "Testable Architecture Design for Programmable Cellular Automata on FPGA Using Run-Time Dynamically Reconfigurable Look-Up Tables", Journal of Electronic Testing, Theory and Applications (JETTA), vol. 36, no. 4, pp. 519-536. (2020)
J5: Ayan Palchaudhuri and Anindya Sundar Dhar, “Fault Localization and Testability Approaches for FPGA Fabric Aware Canonic Signed Digit Recoding Implementations”, Journal of Electronic Testing, Theory and Applications (JETTA), vol. 35, no. 6, pp. 779-796. (2019)
J4: Ayan Palchaudhuri and Anindya Sundar Dhar, “Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies”, Journal of Parallel and Distributed Computing (special issue on Parallel Computing in Modelling and Simulation) (JPDC), vol. 130, pp. 110-125. (2019)
J3: Ayan Palchaudhuri and Anindya Sundar Dhar, “Built-In Fault Localization Circuitry for High Performance FPGA Based Implementations”, Journal of Electronic Testing, Theory and Applications (JETTA), vol. 33, no. 4, pp. 529-537. (2017)
J2: Ayan Palchaudhuri, Amrit Anand Amresh and Anindya Sundar Dhar, “Efficient Automated Implementation of Testable Cellular Automata Based Pseudorandom Generator Circuits on FPGAs”, Journal of Cellular Automata (JCA), vol. 12, no. 3-4, pp. 217-247. (2017)
J1: Rajat Subhra Chakraborty, Indrasish Saha, Ayan Palchaudhuri and Gowtham Kumar Naik, “Hardware Trojan Insertion by Direct Modification of FPGA Configuration Bitstream”, IEEE Design & Test, vol. 30, no. 2, pp. 45-54. (2013)
Conference Proceedings
C19: Suprabhat Bhattacharjee and Ayan Palchaudhuri, “FPGA Optimized Pipelined Modulo Computation Architecture Leveraging Primitive Instantiation and Placement Constraints for Efficient Logic Packing”, 39th International Conference on VLSI Design (VLSID), Pune, India, January 3-7, pp. 215-220. (2026)
C18: Soham Adhikary and Ayan Palchaudhuri, “Fast Bit-Sliced VLSI Architectures on FPGA for Montgomery Domain Modular Inversion”, 38th International Conference on VLSI Design (VLSID), Bengaluru, India, January 4-8, pp. 433-438. (2025)
C17: Santosh Kumar and Ayan Palchaudhuri, “Leveraging Dual Output LUTs with Pipelining for Efficient BCD to Binary Converter on FPGA”, 38th International Conference on VLSI Design (VLSID), Bengaluru, India, January 4-8, pp. 493-498. (2025)
C16: Santosh Kumar and Ayan Palchaudhuri, “Exploring Efficient BCD to Binary Conversion Architecture Alternatives on FPGA”, 31st IEEE International Conference on High Performance Computing, Data and Analytics (HiPC) - Workshops, Bangalore, India, December 18-21, pp. 117-118. (2024)
C15: Ayan Palchaudhuri and Anindya Sundar Dhar, "FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation", 37th International Conference on VLSI Design (VLSID), Kolkata, India, pp. 617-622. (2024)
C14: Ayan Palchaudhuri and Anindya Sundar Dhar, "Primitive Instantiation for Speed-Area Efficient Architecture Design of Cellular Automata based Mageto Logic on FPGA with Built-In Testability", 28th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Fayetteville, Arkansas, USA, pp. 207. (2020)
C13: Ayan Palchaudhuri, Sandeep Sharma and Anindya Sundar Dhar, "Placement Aware Design and Automation of High Speed Architectures for Tree-Structured Linear Cellular Automata on FPGAs with Scan Path Insertion”, 28th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Seaside, California, USA, pp. 316. (2020)
C12: Ayan Palchaudhuri and Anindya Sundar Dhar, “FPGA Fabric Conscious Design and Implementation of Speed-Area Efficient Signed Digit Add-Subtract Logic through Primitive Instantiation”, 53rd Annual Asilomar Conference on Signals, Systems, and Computers (ACSSC), Pacific Grove, CA, USA, pp. 1555-1559. (2019)
C11: Ayan Palchaudhuri and Anindya Sundar Dhar, “VLSI Architectures for Jacobi Symbol Computation”, 32nd International Conference on VLSI Design (VLSID), New Delhi, India, pp. 335-340. (2019)
C10: Ayan Palchaudhuri and Anindya Sundar Dhar, “Redundant Binary to Two’s Complement Converter on FPGAs through Fabric Aware Scan Based Encoding Approach for Fault Localization Support”, IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 25th Reconfigurable Architectures Workshop (RAW), Vancouver, British Columbia Canada, pp. 218-221. (2018)
C9: Ayan Palchaudhuri and Anindya Sundar Dhar, “Fast Carry Chain based Architectures for Two's Complement to CSD Recoding on FPGAs”, 14th International Symposium on Applied Reconfigurable Computing (ARC), Santorini, Greece, pp. 537-550. (2018)
C8: Ayan Palchaudhuri and Anindya Sundar Dhar, “High Speed FPGA Fabric Aware CSD Recoding with Run-time Support for Fault Localization”, 31st International Conference on VLSI Design (VLSID), Pune, India, pp. 186-191. (2018)
C7: Ayan Palchaudhuri and Anindya Sundar Dhar, “Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs”, 24th IEEE International Conference on High Performance Computing (HiPC), Jaipur, India, pp. 104-113. (2017)
C6: Ayan Palchaudhuri and Anindya Sundar Dhar, “Primitive Instantiation Based Fault Localization Circuitry for High Performance FPGA Designs”, 21st International Symposium on VLSI Design and Test (VDAT), Roorkee, India, pp. 594-606. (2017)
C5: Ayan Palchaudhuri and Anindya Sundar Dhar, “High Performance Bit-Sliced Pipelined Comparator Tree for FPGAs”, 20th International Symposium on VLSI Design and Test (VDAT), Guwahati, India, pp. 1-6. (2016)
C4: Ayan Palchaudhuri and Anindya Sundar Dhar, “Efficient Implementation of Scan Register Insertion on Integer Arithmetic Cores for FPGAs”, 29th International Conference on VLSI Design (VLSID), Kolkata, India, pp. 433-438. (2016)
C3: Ayan Palchaudhuri, Rajat Subhra Chakraborty and Durga Prasad Sahoo, “Automated Design of High Performance Integer Arithmetic Cores on FPGA”, 18th Euromicro Conference on Digital System Design (DSD), Madeira, Portugal, pp. 322-329. (2015)
C2: Ayan Palchaudhuri, Rajat Subhra Chakraborty, Mohammad Salman, Sreemukh Kardas and Debdeep Mukhopadhyay, “Highly Compact Automated Implementation of Linear CA on FPGAs”, Cellular Automata - 11th International Conference on Cellular Automata for Research and Industry (ACRI), Krakow, Poland. Published in Lecture Notes on Computer Science, Springer, vol. 8751, pp. 388-397. (2014)
C1: Sanjay Burman, Ayan Palchaudhuri, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay and Pranav Singh, “Effect of Malicious Hardware Logic on Circuit Reliability”, 16th International Symposium on VLSI Design and Test (VDAT), Shibpur, India. Published in Lecture Notes on Computer Science, Springer, vol. 7373, pp. 190-197. (2012)
Patent
Rajat Subhra Chakraborty and Ayan Palchaudhuri, “Architecture and Design Automation of High Performance Large Adders and Counters on FPGA through Constrained Placement”, International PCT application filed in April 2014 (Ref: PCT/IB2014/060372). Indian Patent filed in February 2014 (Ref: 179/KOL/2014).
Book
Ayan Palchaudhuri and Rajat Subhra Chakraborty, “High Performance Integer Arithmetic Circuit Design on FPGA- Architecture, Implementation and Design Automation,” Springer, ISBN 9788132225195 (print), 9788132225201 (ebook) (2016)
Book Chapter
Ayan Palchaudhuri and Rajat Subhra Chakraborty, “A Fabric Component based Approach to the Architecture and Design Automation of High Performance Integer Arithmetic Circuits on FPGA”, in M. Fakhfakh, E. Tlelo-Cuautle and P. Siarry (ed.), “Computational Intelligence in Electronic Design – Digital and Network Designs and Applications”, Springer (Switzerland), ISBN 978-3-319-20070-5 (print), 978-3-319-20071-2 (ebook) (2015)
Conference Presentations
P5: [Best Poster Award] Ayan Palchaudhuri, Sandeep Sharma and Anindya Sundar Dhar, "FPGA Fabric Conscious High Speed Design and Scan Insertion through Efficient Logic Utilization", 12th Student Research Symposium (SRS) of the 26th IEEE International Conference on High Performance Computing (HiPC), Data and Analytics, Hyderabad, India. (2019)
P4: Ayan Palchaudhuri, "FPGA Implementation of High Performance Testable Logic Insertion in Bit-Sliced Architecture Design", 28th IEEE Asian Test Symposium, Semi-Final of 2020 TTTC’s E. J. McCluskey Doctoral Thesis Award, Kolkata, India. (2019)
P3: Ayan Palchaudhuri and Anindya Sundar Dhar, “FPGA Fabric Aware Design of VLSI Architectures”, PhD Forum of the 30th International Conference on VLSI Design (VLSID), Hyderabad, India. (2017)
P2: Ayan Palchaudhuri and Rajat Subhra Chakraborty, “Architecture and Design Automation of High Performance Arithmetic Architectures on FPGAs”, User/Designer Track of the 28th International Conference on VLSI Design, Bangalore, India. (2015)
P1: [Best Poster Award] Ayan Palchaudhuri and Rajat Subhra Chakraborty, “High Performance Integer Arithmetic Circuit Design on Reconfigurable Computing Platforms”, 7th Student Research Symposium (SRS) of the 21st IEEE International Conference on High Performance Computing (HiPC) , Goa, India. (2014)