Implementation of Superscalar Architecture for ARMv4 ISA
This project aims at implementation of Superscalar Architecture for ARMv4 Instruction Set Architecture efficiently on FPGA. It uses the concept of Super Scalar (Tagging, Reservation Stations, Reorder Buffers and multiple execution units) for non-superscalar friendly ISA and shows the benefit over single pipelined Architecture. Architecture has five stage deep and three parallel pipelines for execution.
Implementation of number of different execution units in each pipe stage is done based on our general analysis. It’s not derived from any PD Spec benchmarks. The complete Project is developed on Xilinx 9 and ported on Spartan 3A starter kit.
Complete VHDL code for the project is available.