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8. Digitizer for Point of Care Ultrasound (PDEng thesis)
This work aims to realize an initial step towards developing an ASIC (Application specific Integrated Circuit) for Ultrasound in-probe implementation, with a focus on low power consumption and a small chip area. The primary function of the prototype ASIC is to validate the various required sub-blocks in a single analog front-end (AFE) chain for later implementation at an array level for the final envisioned chip.
PDEng_thesis_AshwinBhat_v1.4.pdf7. Reference voltage generator Simulations & Measurements
A Reference voltage generator (RVG) is needed for the generation of a stable reference voltage for the Analog to digital converter (ADC). This paper presents the simulations & measurements of two ultra-low power 65nm CMOS RVG designs. The designs can operate from a minimum VDD = 0.6V with power consumption of < 100nW. Two RVG designs, one with p+ poly resistor & other with diode connected PMOS are simulated and measurements are carried out on the taped out chips. Finally, a modification to the existing RVG design is also proposed which addresses the RVG output variation over temperature while retaining the power consumption of < 100nW.
5LFF0_ABhat_1v1.pdf6. High Speed DACs
High speed DACs were designed using 45nm FreePDK from NCSU, for high data rate transmitters. The design was verified at schematic level.
5. Systems on Silicon project
In this project, first the Logic synthesis of a MIPS processor was carried out. Next a step-by-step execution of the place and route process using the Cadence SOC Encounter software was done. The final design is verified using Cadences NC-sim digital simulator and Cadence Encounter Timing System (ETS) to do timing signoff.
Final Report Logic Synthesis.pdf5LID0-Lab_2_P+R.pdf4. Low Power 12b SAR ADC for 3D Ultrasound (MSc Thesis)
Low Power 12b SAR ADC for 3D Ultrasound.pdfA system level study with front end analysis of 3D Ultrasound Imaging system with emphasis on deriving specifications and design of a 12 bit Successive Approximation Register (SAR) ADC in 65nm CMOS. The differential SAR ADC has a Capacitive DAC (CDAC) with 4 custom designed unit capacitors intended to simultaneously achieve both matching and area requirements. Monotonic switching scheme with split capacitors ensures stable common mode voltage at CDAC output during the conversion. Single bit Redundancy in CDAC further relaxes the CDAC settling requirement, and along with the high speed, low power Dynamic comparator, enables the design to achieve higher sampling speeds. The designed SAR ADC consumes 243µW operating at 20MS/s with an energy efficiency of 5.97fJ/conversion-step.
3. A 5b 1GHz, Low power Flash ADC for WBAN
A 5b 1GHz, Low power Flash ADC for WBAN.pdfA novel 5-bit 1GHz Flash ADC intended for WBAN applications. TIQ comparators were used to validate proof of concept and reduce design complexity. The ADC was realized in 45nm CMOS with an ENOB:4.35bits and FOM:74fJ/conv
2. Ultra-Low Power Wireless Link system formulation with LNA Design for Receiver in 65nm
5TT40_System.pdf5TT40_LNA.pdfThe application for which the transceiver of this assignment is intended to be used is a wireless in-house sensor system that tracks presence of people in the home, the status of all switches, doors, windows, actuators, energy consumption of all wall outlets, movement of pets, stock in the refrigerator, etc. through approximately 1000 sensors. Obviously, these sensors need to be wireless to make installation feasible, and they need to be very low power so that they do not require battery replacement/recharging all the time. Therefore, they need to work reliably across a distance of up to 10m with a power of less than 10pJ/bit for the receiver and less than 10pJ/bit for the transmitter of the wireless sensor, in both cases for the power dissipation between the data converter and the antenna. System specifications were formulated and a LNA (2 stage cascode with source degeneration) was designed. Specifications and results can be found below.
1. SAR ADC Measurements, Analysis & Modeling
SAR_ADC_Measurements_Analysis_&_modeling.pdfIn this project, a 9bit 1-10MS/s asynchronous SAR low power analog to digital converter (ADC) is studied and measured. The design is based on the one described by Pieter Harpe et al. in “A 12fJ/Conversion-Step 8bit 10MS/s Asynchronous SAR ADC for Low Energy Radios”. To begin with, a literature overview is made. Afterwards, a short summary of the used architecture is presented. Next, two sets of performed measurements will be discussed in detail to determine the ADC behavior. Firstly, a study of the variation of INL/DNL for 8 different chips was performed in order to investigate mismatch effects. Then, INL/DNL, maximum Fs (sampling frequency), power consumption, SNDR, SFDR and ENOB measurements were made for different temperature. Theoretical hypotheses to explain the results found are presented, while confirmation of the same is made using simulation tools with transistors from the TSMC 65nm library.
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