Publications

The following PDFs are provided for reference only. Please respect all copyrights.

A. Farmahini-Farahani, S. Gurumurthi, G. Loh, and M. Ignatowski, “Challenges of High-capacity DRAM Stacks (HBM) and Potential Directions,” Workshop on Memory Centric High Performance Computing held in conjunction with SuperComputing, Nov 2018. [pdf] and [proceedings] and [slides]

F, Khorasani, H. Asghari Esfeden, A. Farmahini-Farahani, N. Jayasena, and V. Sarkar, "RegMutex: Inter-Warp GPU Register Time-Sharing" in ISCA, June 2018. [lightning video] and [slides] and [pdf].

Z. Liu, A. Farmahini-Farahani, and N. Jayasena, "Opportunities for Processing Near Non-Volatile Memory in Heterogeneous Memory Systems," in Workshop on Hardware/Software Techniques for Minimizing Data Movement in conjunction with PACT, 2017. [pdf] and [slides]

A. Farmahini-Farahani, D. Roberts, and N. Jayasena, "Analytical Study on Bandwidth Efficiency of Heterogeneous Memory Systems," in Intl. Symp. on Memory Systems (MEMSYS), pp. 104-118, Oct. 2016. [pdf and ACM link]

H. Asghari-Moghaddam, A. Farmahini-Farahani, K. Morrow, J. H. Ahn and N. S. Kim, "Near-DRAM Acceleration with Single-ISA Heterogeneous Processing in Standard Memory Modules," in IEEE Micro, vol. 36, no. 1, pp. 24-34, Jan.-Feb. 2016. [pdf and link]

N. Jayasena, D. Zhang, A. Farmahini-Farahani, M. Ignatowski, "Realizing the Full Potential of Heterogeneity through Processing in Memory," in Workshop on Near Data Computing in conjunction with MICRO, Dec. 2015. [pdf]

D. Roberts, A. Farmahini-Farahani, K. Cheng, N. Hu, D. Mayhew, M. Ignatowski, "NMI: A New Memory Interface to Enable Innovation," in HotChips, 2015. [pdf and pdf]

A. Farmahini-Farahani, J. Ahn, K. Morrow, and N. S. Kim, "NDA: Near-DRAM Acceleration Architecture Leveraging Commodity DRAM Devices and Standard Memory Modules," in IEEE Symp. on High Performance Computer Architecture (HPCA), 2015. [pdf and pdf and pdf]

A. Farmahini-Farahani, J. Ahn, K. Morrow, and N. S. Kim, "DRAMA: An Architecture for Accelerated Processing near Memory," in IEEE Computer Architecture Letters (CAL), 2014. [pdf and pdf and pdf]

A. Farmahini-Farahani, N. S. Kim, and K. Morrow, "Energy-Efficient Reconfigurable Cache Architectures for Accelerator-Enabled Embedded Systems," in IEEE Intl. Symp. on Performance Analysis of Systems and Software (ISPASS), Mar. 2014. [pdf and pdf and pdf]

P. Aguilera, J. S. Lee, A. Farmahini-Farahani, N. S. Kim, and K. Morrow, "Process Variation-aware Workload Partitioning Algorithms for GPUs Supporting Spatial Multitasking," in IEEE/ACM Design Automation and Test in European (DATE), Mar. 2014. [pdf and pdf]

A. Farmahini-Farahani, H. Duwe, M. Schulte, and K. Morrow, “Modular Design of High-throughput, Low-latency Sorting Units,” IEEE Trans. on Computers, vol. 62, no. 7, pp. 1389-1402, July 2013. [pdf and pdf and pdf]

P. Klabbers, M. Bachtis, J. Brooke, M. Cepeda Hermida, K. Compton, S. Dasu, A. Farmahni-Farahani, S. Fayer, R. Fobes, R. Frazier, C. Ghabrous, T. Gorski, A. Gregerson, G. Hall, C. Hunt, G. Iles, J. Jones ,C. Lucas, R. Lucas, M. Magrans, D. Newbold, I. Oljavo, A. Perugupalli, M.Pioppi, A. Rose, I. Ross, D. Sankey, M. Schulte, D. Seemuth, W.H. Smith, J. Tikalsky, A. Tapper and T. Williams, "CMS Level-1 Upgrade Calorimeter Trigger Prototype Development", J. of Instrumentation, vol. 8, no. 2, Feb. 2013. [link]

K. Compton, S. Dasu, A. Farmahini-Farahani, S. Fayer, R.Fobes, R. Frazier, T. Gorski, G. Hall, G. Iles, J. Jones, P. Klabbers, D. Newbold, A. Perugupalli, S. Rader, A. Rose, D. Seemuth, W. Smith and J. Tikalsky, "The MP7 and CTP-6: Multi-hundred Gbps Processing Boards for Calorimeter Trigger Upgrades at CMS," J. of Instrumentation, vol. 7, no. 12, Dec. 2012. [link]

P. Klabbers, T.Gorski, M. Bachtis, K.Compton, S.Dasu, A. Farmahini-Farahani, R. Fobes, A. Gregerson, M. Grothe, I. Ross, D. Seemuth, M. Schulte and W.H. Smith, "CMS Calorimeter Trigger Phase I upgrade," J. of Instrumentation, vol. 7, no. 1, Jan. 2012. [link]

A. Farmahini-Farahani, A. Gregerson, M. Schulte, and K. Compton, “Modular High-throughput and Low-latency Sorting Units for FPGAs in the Large Hadron Collider,” in Proc. IEEE Intl. Conf. on Application Specific Processors (SASP), San Diego, CA, June 2011, pp. 38-45. Nominated for best paper award [pdf and pdf]

A. Farmahini-Farahani, S. Vakili, S. M. Fakhraie, S. Safari, and C. Lucas, “Parallel Scalable Hardware Implementation of Asynchronous Discrete Particle Swarm Optimization,” Elsevier J. of Engineering Applications of Artificial Intelligence (EAAI), vol. 23, no. 2, pp. 177-187, Mar. 2010. [pdf and pdf and pdf]

A. Farmahini-Farahani, C. Tsen, and K. Compton, “FPGA Implementation of a 64-Bit BID-Based Decimal Floating-Point Adder/Subtractor,” in Proc. IEEE Intl. Conf. on Field-Programmable Technology (FPT), Sydney, Australia, Dec 2009, pp. 518-521. [pdf and pdf]

A. Gregerson, A. Farmahini-Farahani, W. Plishker, Z. Xie, K. Compton, S. Bhattacharyya, and M. Schulte, “Advances in Architectures and Tools for FPGAs and their Impact on the Design of Complex Systems for Particle Physics,” in Typical Workshop on Electronics for Particle Physics (TWEPP), Sep. 2009, Paris, France, pp. 617-626. [pdf and pdf]

A. Gregerson, A. Farmahini-Farahani, B. Buchli, S. Naumov, M. Bachtis, K. Compton, M. Schulte, W. Smith, and S. Dasu, “FPGA Design Analysis of the Clustering Algorithm for the CERN Large Hadron Collider,” in Proc. IEEE Intl. Symp. on Field-Programmable Custom Computing Machines, Napa, CA, Apr. 2009. [pdf and pdf]

A. Farmahini-Farahani, S. M. Fakhraie, and S. Safari, “Scalable Architecture for on-Chip Neural Network Training using Swarm Intelligence,” in Proc. of the Design, Automation and Test in Europe Conf. (DATE’08), Munich, Germany, Mar. 2008, pp. 1340-1345. [pdf and pdf and pdf]

M. Ghaffari-Miab, A. Farmahini-Farahani, R Faraji-Dana, and C. Lucas, “An Efficient Hybrid Swarm Intelligence-Gradient Optimization Method for Complex Time Green's Functions of Multilayer Media,” Progress In Electromagnetics Research (PIER), vol. 77, pp. 181-192, 2007. [pdf and pdf]

A. Farmahini-Farahani, S. M. Fakhraie, and S. Safari, “SOPC-Based Architecture for Discrete Particle Swarm Optimization,” in Proc. IEEE Intl. Conf. on Electronics, Circuits and Systems (ICECS), Marrakech, Morocco, Dec. 2007, pp. 1003-1006. [pdf and pdf and pdf]

N. Sedaghati-Mokhtari, M. N. Bojnordi, A. Farmahini-Farahani, M. Mousavinezhad, and S. M. Fakhraie, “Simulation of Voice Processing Applications through VLIW DSP Architectures,” in Proc. IEEE Intl. Conf. on Electronics, Circuits and Systems (ICECS), Marrakech, Morocco, Dec. 2007, pp. 291-293.

A. Farmahini-Farahani, M. Laali, A. Moghimi, S. M. Fakhraie, and S. Safari, “Mesh Architecture for Hardware Implementation of Particle Swarm Optimization,” in Proc. IEEE Intl. Conf. on Intelligent & Advanced Systems, Kuala Lumpur, Malaysia, Nov. 2007., pp. 1300-1305. [pdf and pdf]

A. Naghdinezhad, A. Farmahini-Farahani, M. R. Hashemi, and O. Fatemi, “An Adaptive Unequal Error Protection Method for Error Resilient Scalable Video Coding Using Particle Swarm,” in Proc. IEEE Intl. Conf. on Signal Processing and Communication, Dubai, UAE, Nov. 2007, pp. 396-399. [pdf and pdf]

H. Assasi, A. Farmahini-Farahani, M. Hamzeh, S. Mohammadi, and C. Lucas, “Input Stimuli Evolution for RFID Tag Functional Verification,” in Proc. Intl. Conf. on RFID Eurasia, Istanbul, Turkey, Sep. 2007, pp. 1-6. [pdf and pdf]

A. Farmahini-Farahani, M. Kamal, S. M. Fakhraie, and S. Safari, “HW/SW Partitioning using Discrete Particle Swarm,” in Proc. ACM Great Lakes Symp. on VLSI, Stresa-Lago Maggiore, Italy, Mar. 2007, pp. 359-364. [pdf and pdf and pdf]

A. Farmahini-Farahani and S. M. Fakhraie, “SOPC-Based Particle Swarm Optimization,” in Proc. Intl. CSI Computer Conf., Tehran, Iran, Feb. 2007, pp. 1536-1541.

P. Saeedi, A. Farmahini-Farahani, M. Hamzeh, M. H. Neishabouri, and A. Afzali-Kusha, “Network-On-Chip Thermal-Balanced Mapping,” in Proc. IEEE Design and Test Workshop, Dubai, UAE, Nov. 2006.

A. Farmahini-Farahani, M. Kamal, and M. Salmani-Jelodar, “Parallel-Genetic-Algorithm-Based HW/SW Partitioning,” in Proc. Intl. Symp. Parallel Computing in Electrical Engineering, Poland, Sep. 2006, pp. 337-342. [pdf and pdf]

M. Kamal, A. Farmahini-Farahani, and M. Salmani-Jelodar, “Automatic Combinational Circuit Design using Genetic Algorithm,” in Proc. Conf. Intelligent Systems, Tehran, Iran, 2005 (Persian).