I am a computer architect mainly working on technical challenges of memory systems (including HBM) and their potential solutions with a focus on high-performance computing, machine intelligence, and deep neural networks. I am currently employed by Google Cloud in Sunnyvale, CA and was formerly employed by AMD Research in Santa Clara, CA. I can be reached through LinkedIn.
Research Summary: computer architecture as a whole, processing near memory, memory systems, in-package 3D-stacked memory, high-bandwidth memory (HBM), heterogeneous and multi-level memory architectures, networks of memory elements, abstracted memory interfaces, DDR-based interfaces, commodity and stacked DRAM, non-volatile memory, memory controller capability enhancement, machine intelligence and neural network processing architectures, memory hierarchy design for neural networks, etc.
Involves power/energy estimates and analysis, performance measurements (latency, bandwidth, execution time, etc.), application-driven and application-independent study, simulation/spreadsheet/back-of-the-envelope analysis, architecture-level modeling, analytical modeling, use case evaluation, OS/programmability impact study, area and capacity estimates, etc.
Past research: FPGA design, reconfigurable accelerator design, large hadron collider (LHC), hardware design and implementation of bio-inspired algorithms (neural networks, swarm intelligence, genetics intelligence)
Education
Ph.D. in Electrical and Computer Engineering from University of Wisconsin-Madison
M.Sc. in Electrical and Computer Engineering from University of Wisconsin-Madison
M.Sc. in Computer Engineering from University of Tehran
B.Sc. in Computer Engineering from Iran University of Science and Technology
Disclaimer: This is a personal webpage. The views and opinions expressed here represent my own and not those of my employer.