Yield Learning

Advancing Yield Learning

• Configuring and running operations in volume diagnostics for logic scan, boundary scan, package tests to generate faillog from STDF.

• Integration of inputs from PD/layout (LEF/DEF files), DFT (flattened netlist, STIL, tcd, patdb, spr) and Test Engineering (STDF files) to generate fail log files while handling the multiple opportunities for error.

• Running the diagnostics tool to get the callouts for the die of the wafer.

• Observing the process flow on the IT infrastructure to mitigate the risks.

• Loading the Yield Engineering tool for the Lot, Wafer and Die information per wafer at the earliest possible instance with cross-functional FMEA.