VLSI Lab INFORMATION


DO’S AND DON’Ts IN THE LABORATORY

* Students are expected to come in proper dress code to Lab, as prescribed by the college.

* Students are expected to come with complete preparation to the lab (Lab Manual, Laptop, etc.)

* Bags are not allowed inside the Lab.

* It is the responsibility of the students to see that the components of the Lab are in working condition, before and after experiments.

* Any damage to a device or system shall be borne by the students.

* Read the theory of the experiment to be performed, well in advance and understand the working principle clearly, before conducting the experiment.

* Come prepared for viva - voce.

* Follow the given procedure in the same sequence.

* Handle the equipment with care.

* Systems are to be checked for correctness before conduction of experiments.

* Don’t switch on the power supply while making the connection.


LIST OF EXPERIMENTS

Analog Design

1.Design a CMOS inverter and Simulate for transient characteristics and DC analysis.

2.Design and simulation of static characteristics of two input NAND gate

3.Design and simulation of static characteristics of two input NOR Gate

4. To design a Common Source Amplifier with given specifications and simulate for DC analysis, AC analysis and Transient analysis.

5.To design a Common Drain Amplifier with given specifications, and simulate for DC analysis, AC analysis and Transient analysis.

6.Design and simulation of static characteristics of two input AND Gate & OR Gate.

Digital Design

7.To Compile and simulate the Verilog Code for an inverter circuit and observe the waveform.

8.To write Verilog Code for the Buffer circuit and Test Bench for Verification, observe the waveform.

9.To write Verilog Code for the Transmission gate circuit and Test Bench for Verification, observe the waveform.

10.Realization and Simulation of D flip flop using Transmission gate.


Open ended experiments

11.Creating a Layout for CMOS inverter.

12.To design 4 bit R-2R DAC using Op-amp with given specification

13.To design a single stage differential amplifier with given specifications, and simulate for DC analysis, AC analysis and Transient analysis.

Lab Manual

VLSI (18EI54) LAB MANUAL.pdf

LAB Experiments Videos

Prog-2 Verilog

buffer.avi

Exp1: Inverter Design

Exp2: NAND Gate Design

Exp.3 NOR Gate Design