3DML: Open-Source
For the first time, we release datasets for Coherent vs. Non-Coherent MU-MIMO with Uplink Data to experiment with distributed beamforming in the presence of time and frequency offset.
We have used the RENEW platform to generate extensive datasets containing uplink pilots and actual data OFDM symbols generated from random bits.
We use a 64-antenna RENEW massive MIMO base station in an indoor lab environment, and up to 8 user clients, statically located in the vicinity of the base station.
We collect a massive MIMO channel dataset for examining the inter-user channel correlation in a real-world propagation environment.
We used the Argos V2 platform to measure the mobile channels to a 64-antenna massive MIMO base station in outdoor environments.
We measured user channels in 4 Line-of-Sight and 5 Non-Line-of-Sight clusters in near-stable environments. In each cluster, we measured channels in more than 25 locations.
In total, the measurement covers more than 225 locations. The measured channel at each location covers all 52 data sub-carriers and up to 300 frames. The measurement is done on 2.4-GHz ISM band.
HW-NAS-Bench [ICLR 2021, Spotlight] is the first public dataset for Hardware-Neural Architecture Search aimed at democratizing research to non-hardware experts and make HW-NAS research more reproducible, and accessible for the community. To design HW-NAS-Bench,
We carefully collect the measured/estimated hardware performance (e.g., energy cost and latency) of all the networks in the search spaces of both NAS-Bench-201 and FBNet, on six hardware devices that fall into three categories (i.e., commercial edge devices, FPGA, and ASIC).
We provide a comprehensive analysis of the collected measurements in HW-NAS-Bench to provide insights for HW-NAS research.
We demonstrate exemplary user cases to (i) show that HW-NAS-Bench allows non-hardware experts to perform HW-NAS by simply querying our pre-measured dataset and (ii) verify that dedicated device-specific HW-NAS can indeed lead to optimal accuracy-cost trade-offs.
An automated DNN chip generator for both FPGA and ASIC DNN chip implementation.
A Chip Predictor that can accurately and efficiently predict a DNN accelerator’s energy, throughput, latency, and area based on the DNN model parameters, hardware configuration, technology-based IPs, and platform constraints.
A Chip Builder automatically explores the design space of DNN chips and optimizes chip design via the Chip Predictor, and then generate synthesizable RTL code with optimized dataflows to achieve the target design metrics.
Simulates a QuaDRiGa channel with Generalized Memory Polynomial (GMP)-based Power Amplifiers (PA) and GMP-based Digital Predistortion (DPD) per antenna.
QUAsi Deterministic RadIo channel GenerAtor (QuaDRiGa), is used for generating realistic radio channel impulse responses for system-level simulations of mobile radio networks.