Transistor Shrinking

In the last decade, there have been significant increases in computational power worldwide, thanks to the increased number of devices, as well as the increased complexity of software, especially with the ongoing wave of AI resurgence. In contrast, the entire industry has only increased in power consumption by 6%. This is attributed to node shrinkage.

Modern computer CPUs are composed of billions of transistors, which are little valves that either allow electrons to flow through or not, representing on or off. A few of them can make an AND gate, which produces an output if both inputs are active, or make an OR gate, where an output is produced when at least one of the inputs is active. A handful of these gates can make a circuit to add 2 numbers, and off we go. There is a strong correlation between the number of transistors on a CPU, and the performance of the CPU, which corresponds to the number of instructions it can complete in a second. In 2012, the cutting edge “node” was 22 nanometres, where a “node” refers to a generation of transistor sizes. Since when a chip producer wants to shrink their transistors, new sets of machinery need to be designed, built, and installed. These improvements come in waves, known as “nodes”. We went from 22 nanometre wide transistors to the latest 3nm node.

Or that’s how the narrative goes. In reality, humanity does not have the ability to make transistors that are 3 nanometres wide. The monster science educators have warned of, of a physical limit to how far we can shrink transistors, has appeared, and has been generally ignored. One decade ago, at the 22nm node, we have already hit the size limit for traditional MOSFETs.

These performance improvements, as a result of transistor design changes, improve the overall power consumption of the chip. The current transistor design, FinFET, wraps the “gate” (a conduit, which when a current is passed through it, the transistor stops electrons from flowing through, and when there is no current, the transistor allows electrons to flow.) around the top of a fin of conductive silicon (the channel, where the main current is passed through). Through incremental improvements to chip production techniques, complex 3D structures can be built; and increased surface area between the gate and the main conductor improves power efficiency, delivering performance increases akin to node shrinkage. The ultimate form of the silicon transistor is likely to be the GAAFET, the final trick up our sleeves, where the gate completely envelops the channel. This maximises surface area, and hopefully, by the time the production process for this gate reaches maturity (when the transistor can no longer be further shrunk physically), alternate materials to silicon and alternate computing paradigms will be ripe to transition to.