Speaker 1: Mr. Simon TC Wang (王庭昭)

Bio

王庭昭現任晶心科技資深市場技術經理，在此之前他曾在聯發科及四零四科技擔任軟體架構師。他擁有國立陽明交通大學電控系所學士及碩士學位。 

Abstract

In this presentation, we will dive into how RISC-V is shaking up the AI world by letting developers build exactly what they need. Most importantly, I’m sharing the real-world success story of Andes Technology. We’ll look at how their RISC-V cores are actually powering LLMs today, proving that RISC-V architecture is flexible, extensible, and powerful for the next gen of AI.

Speaker 2: 顏敬哲

Bio

曾任職於聯發科技，從事相機 3A／ISP 軟體開發工作，具備影像處理與系統軟體實務經驗。現任職於晶心科技，專注於 SystemC TLM 系統建模與 toolchain 開發，投入於處理器架構相關的軟體與系統層技術。

Abstract

Compiler optimization often relies on LLVM scheduler models and llvm-mca for pipeline and latency analysis. However, when microarchitectural behavior cannot be fully abstracted—such as multiple execution stages or ambiguous corner-case latencies—static models can diverge from real hardware performance. This talk demonstrates how a cycle-accurate simulator can be integrated into the compiler optimization workflow as a practical analysis tool. Three case studies are presented: When hardware implements separate EX/LX stages but LLVM models only a single execution resource, simulation helps analyze stage contention and guide scheduler tuning. When reduction instruction latencies are unclear in the hardware specification, simulation enables more accurate scheduling decisions. In an AI kernel acceleration case, simulation exposes the true bottleneck, motivates the introduction of a custom instruction, and verifies the resulting performance gain. The methodology can be combined with LLVM LNT and automated workflows to accelerate optimization iterations. Compared to costly and time-consuming FPGA validation, a pure software cycle-accurate simulator enables lower-cost, faster experimentation in early development stages. Ultimately, a cycle-accurate simulator bridges the gap between microarchitecture and compiler optimization. By grounding compiler decisions in real hardware behavior, developers can achieve greater accuracy and faster iteration cycles, ensuring that software is truly tuned for the silicon it runs on.

Speaker 3: Dr. Rogers Heng-Kuan Lee (李恒寬)

Bio

交通大學博士，曾任職於智原科技、創意電子及聯詠科技，從事多媒體壓縮、訊號處理與電腦視覺相關研究與開發工作。現任晶心科技運算加速研發處副處長，專注於人工智慧相關技術與應用開發。 

Abstract

The exponential function is a key computational component in large language model (LLM) workloads, particularly in softmax and attention operations. Efficient and flexible implementations are critical for meeting diverse accuracy, latency, and hardware requirements in AI systems. This work explores multiple approximation techniques for the exponential function, including polynomial and table-based methods, and evaluates their trade-offs in numerical accuracy and computational cost. We introduce an AI-assisted development flow that generates both C reference code and synthesizable Verilog RTL from mathematical specifications. The generated designs are integrated into the Andes ACE workflow for system-level verification. This study demonstrates a practical methodology that can be adapted to different design objectives, allowing users to guide and customize parts of the workflow. This approach highlights how AI-assisted generation can accelerate function development, reduce implementation effort, and support integration across diverse software and hardware applications.