Speakers

EDA Industry Perspective on AI/ML Hardware/Software

Abstract: This presentation will discuss requirements for the design of systems on chips (SoCs) and systems for artificial intelligence (AI) and machine learning (ML) and introduce solutions that the Electronic Design Automation (EDA) industry provides today, as well as trends to address future challenges. In addition, we will also introduce AI/ML technologies that are used to increase the productivity and optimize the EDA design processes itself.

Specifically, we will discuss aspects of enabling processor and design IP and high-level synthesis to enable optimized circuitry for AI/ML algorithms. Furthermore, we will introduce the requirements for optimized verification of AI/ML designs and specific optimizations of verification tools for this category of designs. Advanced node and low power implementation will be key aspects linking verification to SoC implementation and we will discuss specific optimizations, as well as 3DIC and Chiplet based integration and analysis aspects. For the utilization of AI/ML for EDA, we will introduce trends and experiences with using AI/ML for formal verification, simulation and implementation.

Effective Co-design of Deep Learning Algorithms and Hardware Accelerators

Abstract: In a conventional top-down design flow, deep-learning algorithms are first designed concentrating on the model accuracy, and then accelerated through hardware accelerators trying to meet various system design targets on power, energy, speed, and cost. However, this approach often does not work well because it ignores the impacts and physical constraints that the hardware architectures themselves would have towards the deep-learning algorithm design and deployment. Thus, an ideal scenario is that algorithms and their hardware accelerators are developed simultaneously. In this talk, we will present our DNN/Accelerator co-design and co-search methods. Our results have shown great promises for delivering high-performance hardware-tailored DNNs and DNN-tailored accelerators naturally and elegantly. One of the DNN models coming out of this co-design method, called SkyNet, won a double championship in the competitive DAC System Design Contest for both the GPU and the FPGA tracks for low-power object detection in 2019.

Design Limits on In-Memory Computing: Beyond the Crossbar

Abstract: AI algorithms have achieved increasingly higher accuracy for a variety of applications, with the cost of deeper networks, larger model size, and higher connection density. RRAM-based IMC architecture offers a parallel and energy-efficient solution. Yet, its performance is limited by device non-idealities, circuit precision, on-chip interconnection, and algorithm properties. Based on statistical data from a fully-integrated 65nm CMOS/RRAM test chip and a cross-layer simulation framework, we illustrate that the real bottleneck of the IMC system is not the RRAM cross-bar, but the analog-to-digital converter (ADC) precision and the stability of machine learning models. These factors interact with device variation and the Roff/Ron ratio, limiting the useful number of RRAM levels, inference accuracy, and system energy-delay product (EDP). In addition, the topology of on-chip interconnect needs to be optimized in order to manage a large volume of data movement among the crossbars. The results are summarized into a roofline model and demonstrated on CIFAR-10, SVHN, CIFAR-100 and ImageNet, helping shed light on future IMC research focus.

AutoQKeras: An AutoML Library for QKeras

Abstract: In this talk, we will introduce AutoQKeras, a library for quantization selection and hyperparameter tuning for Deep Neural Networks. Using AutoQKeras, users can trade-off accuracy by quantization. In order to perform the appropriate trade-offs, we introduce "forgiving factor", which enables a user to answer the question "if I could reduce the model energy or number of bits by a factor, how much accuracy would the user be willing to trade-off". With AutoQKeras, users can select among several optimization strategies, such as global optimization of network hyperparameters and quantizers, or splitting the optimization problems into smaller search problems to cope with search complexity. We show how AutoQKeras and QKeras can be used to create sub-microsecond inference engines.

A Statistical Distribution-based Deep Neuron Network Model – a new perspective on effective learning

Abstract: The impressive results achieved by deep neural networks (DNNs) in various tasks,computer vision in particular, such as image recognition, object detection and image segmentation, have sparked the recent surging interests in artificial intelligence (AI) from both the industry and the academia alike. The wide adoption of DNN models in real-time applications has, however, brought up a need for more effective training of an easily parallelizable DNN model for low latency and high throughput. This is particularly challenging because of DNN's deep structures. To address this challenge, we observe that most of existing DNN models operate on deterministic numbers and process one single frame of image at a time, and may not fully utilize the temporal and contextual correlation typically present in multiple channels of the same image or adjacent frames from a video. Based on well-established statistical timing analysis foundations from the EDA domain, we propose a novel statistical distribution-based DNN model that extends existing DNN architectures but operates directly on correlated distributions rather than deterministic numbers. This new perspective of training DNN has resulted in surprising effects on achieving not only improved learning accuracy, but also reduced latency and increased high throughputs. Preliminary experimental results on various tasks, including 3D Cardiac Cine MRI segmentation, showed a great potential of this new type of statistical distribution-based DNN model, which warrants further investigation.