Implementing and Evaluating Quantum Error Correction Codes

The long-term viability of large-scale quantum computing critically depends on the effective implementation and evaluation of Quantum Error Correction (QEC) codes. While many QEC codes have been proposed, their evaluation has often relied on simplified metrics—most notably, the number of physical qubits required to encode a logical qubit on a given hardware platform. Although qubit count is important, it is only a first-order proxy for overall system cost. In practice, the optimality of a QEC design is multi-dimensional and depends on interacting system-level constraints, including: 

1. Total number of physical qubits

2. Spatial and temporal volume of QEC circuits

3. Threshold and logical error rates

4.  Scheduling efficiency of syndrome extraction

5.  Overheads associated with state distillation or magic-state factories 

6. Decoder performance and real-time constraints. 

Today, the field lacks mature end-to-end methodologies and software infrastructure for systematically implementing, mapping, and comparing QEC codes under realistic architectural assumptions.

Addressing this gap requires close collaboration across quantum information science, systems, and hardware architecture—an intersection that closely aligns with the ISCA community. This tutorial introduces a systems-oriented view of QEC, focusing on how QEC codes are implemented, scheduled, mapped to hardware, and evaluated under realistic constraints.

The tutorial will walk through concrete examples of implementing logical qubits using representative QEC codes, highlighting practical considerations such as lattice surgery, transversal gates, syndrome-extraction scheduling, decoder integration, and real-time constraints. Attendees will learn how architectural choices and scheduling strategies affect logical error rates, thresholds, and overall resource efficiency. The material is designed to be accessible to participants with a systems background and basic familiarity with quantum information concepts. By connecting QEC theory with architectural and runtime realities, the tutorial aims to engage the ISCA community with emerging challenges at the boundary of quantum architecture, compilation, and fault-tolerant system design. 

Tutorial outline:

1. From QEC Theory to Hardware Implementation: logical qubits and code primitives; representative end-to-end QEC implementations.

2. Lattice Surgery and Transversal Operations: principles of lattice surgery; trade-offs in fault-tolerant gate realization.

3. Scheduling QEC Operations: syndrome-extraction scheduling; effects on code distance, threshold, and performance.

4. Mapping QEC to Hardware Architectures: hardware-aware placement and routing; estimation of space–time volume and system cost.

5. Decoding and Real-Time Constraints: stabilizers and decoder integration; latency, throughput, and hardware acceleration.

6. Open Challenges and Research Directions: toolchain gaps, benchmarking challenges, and opportunities for systems and architecture research.

Presenters:  

Steven Hofmeyr, Costin Iancu, Mathias Weiden, Ed Younis - Lawrence Berkeley National Laboratory

Gushu Li - University of Pennsylvania

Yue Wu - Microsoft Quantum

Schedule: