Research

We build the systems software that makes large models fast and affordable to run. Our recent work spans the whole model serving path — how requests are scheduled and how KV cache is managed across multi-turn dialogues (ASPLOS 2025), how pipeline and tensor parallelism should be organized on multi-GPU servers (OSDI 2026), and how models move between host and GPU memory (EuroSys 2023 and TOCS 2026). We also treat GPU memory as a resource to be managed rather than a fixed budget, through harvesting across concurrent jobs (ATC 2022) and tiering over coherent CPU-GPU interconnects such as NVIDIA Grace Hopper (CAL 2025, IEEE Best Paper Award Runner-Up). Ongoing directions include test-time scaling and reasoning, agentic RL training, speculative decoding, prefill-decode disaggregation, and serving on NPUs and PIM.

DRAM density has stopped scaling, so capacity now arrives through new paths such as CXL memory expanders, NUMA-attached far memory, and pools disaggregated across nodes. We revisit how the Linux kernel should manage memory once it is no longer uniform. Our work covers page placement and promotion policy for multi-tiered systems (ATC 2021 and CAL 2020), where remote memory should be placed when several interconnect paths exist (APSys 2021), and how migration itself can be offloaded to hardware such as Intel DSA instead of burning CPU cycles (CAL 2025). We also study segmentation-based translation for LLM inference (CAL 2026), together with CPU scheduling for consolidated servers (EuroSys 2018 and TPDS 2020). Prototypes are built in the Linux kernel and evaluated on real machines.

Modern datacenters no longer run on CPUs alone. We study how GPUs and NPUs should be built for the workloads that now dominate them, and how the memory system underneath has to change to keep those units fed. On the GPU side we examine how streaming multiprocessors, caches, and the memory hierarchy behave under LLM inference and training, and where the right design points sit for multi-tenancy and memory oversubscription. On the NPU and PIM side we look at dataflow, on-chip buffer organization, and which operators belong near memory rather than on the accelerator die. We start from measurements on real machines using hardware performance counters, then explore alternatives in cycle-level simulators such as gem5 and GPGPU-Sim.