DESIGNED PROCESSOR

Processor Execution Flow

1.Program Counter Initialization

1. • The Program Counter (PC) is initialized to the starting address of the program in the Code Memory (ROM). This is managed by the PC Initialization module.

2.Instruction Fetch

1. • The PC provides the current instruction address to the Memory Address Register (MAR).

   • The instruction is retrieved from Code Memory and temporarily stored in the Memory Buffer Register (MBR).

   • The MBR transfers the instruction to the Instruction Register (IR) for decoding.

3.Instruction Decode

1. • The Decode Unit processes the instruction in the IR and separates it into:

     • Opcode (OP): Specifies the operation (e.g., LOAD, STORE, ADD).

     • Operand: Indicates the memory address or register to be accessed.

   • In direct addressing mode, the operand directly represents a memory address.

4.Operand Fetch

1. • For instructions requiring memory data:

     • The operand (memory address) is sent to the MAR.

     • A read signal (RW) fetches data from the specified Data Memory (RAM) address.

     • The fetched data is loaded into a temporary register for further processing.

5.Execution

1. • The processor performs the operation based on the opcode:

     • LOAD: Transfer data from memory to a register.

     • STORE: Write data from a register to memory.

     • Arithmetic/Logical Operations: The Arithmetic Logic Unit (ALU) processes data from source registers (e.g., RA, RB) and stores the result in the destination register (RZ).

6.Write Back

1. • For instructions like STORE, the result in RZ is written back to memory:

     • The MAR holds the target memory address.

     • A write signal (RW) initiates the data transfer to memory.