Instruction Sizes
32-bit (ARM), 16-bit (Thumb), and mixed (Thumb-2).
Data Types
short ints, at least 16 bits [ARM: half-word]
chars, at least 8 bits [ARM: byte]
ints, at least 16 bits [ARM: word]
long ints, at least 32 bits [ARM: word](all the above signed or unsigned)
floating-point, double, long double, enumerated types, bit fields
Instruction Types
Data Processing: Arithmetic and logic (e.g., ADD, SUB).
Load/Store: Memory operations (e.g., LDR, STR).
Branch: Control flow (e.g., B, BL).4
Addressing Modes
1. Immediate Addressing : data (only 1 byte) is specified in the instruction
MOV R5, #0x20 ; 20H will be copied to R5
2. Register Addressing : data is given by registers only
MOV R5, R1 ; R1 will be copied to R5
3. Direct Addressing : address of operand is given in instruction, address will be 12 bits offset from PC given by assembler
LDR R5, Variable(LABEL) ; R5 <- [Variable]
4. Indirect Addressing : Address of operand is given by register
LDR R5, [R1] ; R5 <- [R1]
i. Register relative indirect addressing mode : address of memory operand = register + Numeric Value
LDR R0, [R1, #0x04] ; R0 <- data from mem pointed by (R1+4), here R1 remains unchanged
a)Pre-Indexing:
LDR R0, [R1, #0x04]! ; first, R1<-R1+4
then, R0 <- data from mem pointed by (R1)
b)Post-Indexing:
LDR R0, [R1], #0x04 ; First, R0 <- [R1]
then, R1<-R1+4
ii. Base Indexed Indirect Addressing: Here address of the memory operand is given by a sum of two registers
First register acts as base, second acts as index register
LDR R0, [R1, R2] ; R0 <- data form mem pointed by (R1+R2)
a)Pre-Indexing:
LDR R0, [R1, R2]! ;First, R1 <- R1+R2
then, R0<- data from mem pointed by (R1)
b)Post-Indexing:
LDR R0, [R1}, R2 ; First, R0 <- [R1]
then, R1<-R1+R2
iii. Base with scaled index indirect addressing: here address of the mem operand is given by a sum of two registers, where first reg acts as base
and second reg scaled index by shift left
LDR R0, [R1, R2, LSL #2] ; R0<- data from mem pointed by (R1 + R2 shifted left by 2 bits, R1 remains
unchanged