Learning Outcome:
Gain a solid understanding of various instruction formats for multiple addressing modes, including immediate, direct, register, and indirect addressing. Implement a complete instruction lifecycle involving fetch, decode, execute, and write-back phases.
Tasks:
Define the instruction formats for different addressing modes: immediate, direct, register, and indirect.
Simulate the full instruction lifecycle, encompassing the fetch-decode-execute-write back stages.
Description:
Indirect addressing mode refers to a method in computer architecture where the instruction specifies an address that points to another memory location holding the actual operand. The opcode in the instruction indicates the operation to be performed, while the operand field provides a pointer to the memory location containing the address of the data. During execution, the CPU retrieves the address from the specified memory location and then accesses the operand indirectly. This approach adds flexibility by allowing dynamic operand locations but increases the complexity of the instruction execution.
Deliverables:
Logisim simulation files can be downloaded and opened in the Logisim environment.
Working:
Program Counter Initialization:
The Program Counter (PC) is initialized to point to the start address of the program stored in Code Memory (ROM). This initialization is handled by a dedicated PC initialization module.
Instruction Fetch:
The Program Counter (PC) is initialized to point to the start address of the program stored in Code Memory (ROM). This initialization is handled by a dedicated PC initialization module.
Instruction Decode:
The IR now holds the fetched instruction.
The Decode Unit interprets the instruction by dividing it into two parts:
Opcode (OP): Specifies the operation to be performed (e.g., LOAD, STORE, ADD).
Operand: Specifies the address that points to another memory location holding the actual data.
Unlike direct addressing mode, where the operand is directly accessible, in indirect addressing mode, the operand is obtained by first accessing the memory location pointed to by the operand field.
Operand Fetch:
If the instruction involves reading data from memory:
The operand (pointer) from the IR is sent to the MAR.
A read signal (RW) is generated, prompting the Data Memory (RAM) to fetch the address from the specified location.
The fetched address is then used to access the actual data.
The data at the effective address is loaded into a temporary register for further processing.
Execution:
Based on the opcode, the processor performs the desired operation:
LOAD: Transfers data from the effective address to a register.
STORE: Writes data from a register to the memory location pointed to by the effective address.
Arithmetic/Logical Operations: Data from registers RA and RB is sent to the ALU, which performs the required computation and stores the result in register RZ.
Write Back:
For instructions like STORE, the result in register RZ is written back to memory.
The MAR is loaded with the effective address, and a write signal (RW) is triggered to complete the write-back.