Faculty Profile

Dr. Sushanta Kumar Mohapatra

LMCSI, IEEE (Sr. Member), LMISTE, LMIETE, LMOITS

School of Electronics Engineering, Kalinga Institute of Industrial Technology, Bhubaneswar.

Email- sushanta.mohapatrafet@kiit.ac.in, skmctc74@gmail.com , s.k.mohapatra@ieee.org .

Dr. S. K. Mohapatra, received his B.E. from Utkal University, M.E. in Communication Control and Networking from MITS, Gwalior, in 1994 and 2003 respectively. He obtained Ph.D. from National Institute of Technology, Rourkela, in the year 2016. He is currently serving as Assistant Professor in SOEE, KIIT University, Bhubaneswar. His research interests include Modeling and Simulation of Nanoscale Devices and its application in IoT. Energy efficient Wireless Sensor Networking, Adhoc Networks, Cellular Communications, Metamaterial absorbers in THz application, UWB-MIMO Antenna, Reconfigurable Antenna, Performance enhancement for high frequency applications. He has extensively contributed as author and co-author in several national and international journals and conferences of repute. He has been a part of committee member of various international conferences, Editorial Board Member and Reviewer of many international journals. . He is a life member of ISTE, IETE, CSI, OITS and Senior Member of IEEE.

The biography included in the “2016 33^rd edition of the Marquis Who's Who in the World" due to demonstration of outstanding achievement in the field of research, and thereby, contributed significantly to the betterment of contemporary society. During Ph.D. research scholar (Full Time Jul. 2011 to Apr. 2016), he received the “Best Research Presentation” award among all 20 departments of the Institute on occasion of Research Scholar Week-2015, N.I.T., Rourkela. He also received the “Best Paper Award” at International Conference on Microelectronics, Communication and Computation, San Diego, USA. He has extensively contributed as author and co-author in several national and international journals and conferences of repute.

List of Publications – S. K. Mohapatra

2019

Book Chapter

B. Vandana, Prashant Parashar, B. S. Patro, K. P. Pradhan, S. K. Mohapatra, and J. K. Das. "Mole Fraction Dependency Electrical Performances of Extremely Thin SiGe on Insulator Junctionless Channel Transistor (SG-OI JLCT)." In Advances in Signal Processing and Communication, pp. 573-581. Springer, Singapore, 2019. (ISBN 9811325537, 9789811325533)
T. M. Behera, U. C. Samal, and S. K. Mohapatra, "Routing Protocols." Computational Intelligence in Sensor Networks. Springer, Berlin, Heidelberg, 2019. 79-99. DOI-https://doi.org/10.1007/978-3-662-57277-1_4. Print ISBN-978-3-662-57275-7.

Journals

T.M. Behera, S.K. Mohapatra, U.C. Samal, M.S. Khan, M. Daneshmand and A.H. Gandomi,. “I-SEP: An Improved Routing Protocol for Heterogeneous WSN for IoT based Environmental Monitoring.”. IEEE Internet of Things Journal, DOI: 10.1109/JIOT.2019.2940988, Early Access 2019. (IEEE)
D. Dutta, A. Pradhan, O. P. Acharya, and S. K. Mohapatra, “IoT based pollution monitoring and health correlation: a case study on smart city”. International Journal of System Assurance Engineering and Management, 10(4), pp.731-738, 2019. (Scopus) Springer.
S. A. Sahu, R. Goswami, S. K. Mohapatra. “Characteristic Enhancement of Hetero Dielectric DG TFET Using SiGe Pocket at Source/Channel Interface: Proposal and Investigation”. Silicon, 2019. (Scopus/SCI) Springer.
T.M. Behera, S.K. Mohapatra, U.C. Samal, M.S. Khan, “Hybrid heterogeneous routing scheme for improved network performance in WSNs for animal tracking”. Internet of Things, Vol. 6, pp. 100047,June ,2019. (Elsevier) .
T.M. Behera, S.K. Mohapatra, U.C. Samal, M.S. Khan, M. Daneshmand and A.H. Gandomi,. “Residual Energy Based Cluster-head Selection in WSNs for IoT Application”. IEEE Internet of Things Journal, 2019. (IEEE)

2018

Journals

A. Mohanty, O. P. Acharya, B. Appasani, and S. K. Mohapatra. "A multi-band terahertz metamaterial absorber based on a Π and U-shaped structure." Photonics and Nanostructures-Fundamentals and Applications, Vol. 32, pp. 74-80, 2018. (Elsevier).
T. M. Behera, S. K. Mohapatra, and U. C. Samal, “SNRP: Sub-netting based routing protocol for improved network performance in WSN”, International Journal of Advanced Science and Technology, Vol. 121, pp. 31-42, 2018. (SERSC)
S. Mishra, A. Dastidar, U. C. Samal, and S. K. Mohapatra, “Review of different image data hiding techniques”, International Journal of Advanced Science and Technology, Vol. 121, pp. 43-54, 2018. (SERSC)
A Pattnaik, S. K. Mohapatra, “Study of Silicon Body Thickness and Channel Length on SCEs and Electrical Performances of Underlapped GS-DG-MOSFET”, International Journal of Advanced Science and Technology, Vol. 115, pp. 113-124, 2018. (SERSC) (http://dx.doi.org/10.14257/ ijast.2018.115.11)
T. M. Behera, U. C. Samal, and S. K. Mohapatra, "Energy Efficient Modified LEACH Protocol for IoT Application." IET Wireless Sensor Systems, 2018. (IET) ( 10.1049/iet-wss.2017.0099)
Shasanka Sekhar Rout, S. K. Mohapatra, and Kabiraj Sethi. "Design of Cascode Mixer Based on Bulk Injection and Switched Biasing Techniques in 180 nm CMOS Process for a High Performance Receiver Front End." Journal of Low Power Electronics Vol. 14, no. 1, pp. 49-56, 2018. (American Scientific Publisher)
B Vandana, B. S. Patro, J. K. Das, Brajesh Kumar Kaushik and S. K. Mohapatra "Inverted ‘T’Junctionless FinFET (ITJL FinFET): Performance Estimation through Device Geometry Variation." ECS Journal of Solid State Science and Technology Vol.7, No.4: pp. Q52-Q59, 2018.
B Vandana, Jitendra Kumar Das, Sushanta K. Mohapatra, and Suman Lata Tripathi. "Impact of Channel Engineering (Si1-0.25 Ge0. 25) Technique on gm (Transconductance) and Higher Order Derivatives of 3D Conventional and Wavy Junctionless FinFETs (JLT)." Facta Universitatis, Series: Electronics and Energetics 31, no. 2 (2018): 257-265.
Trupti M. Behera, Sushanta K. Mohapatra. "Improving Network Lifetime by Minimizing Energy Hole Problem in WSN for The Application of IoT." Facta Universitatis, Series: Electronics and Energetics 31, no. 2 (2018): 267-277.

Conferences

Shibam Swarup Das, Ruby Mishra, and S. K. Mohapatra. "Design & Performance Analysis of Low Power 1-bit Full Adder at 90 nm node using PTL Logic." In 2018 Second International Conference on Computing Methodologies and Communication (ICCMC), Feb 15, pp. 636-639. IEEE, 2018.

2017

Journals

T. M. Behera, S. K. Mohapatra, and O. P. Acharya. "Performance Analysis of Heterogenous WSN for Application in IoT.", Oriental Journal of Computer Science and Technology, Vol.10, No.4, pp.730-735, 2017.
B Vandana, S. K. Mohapatra, J. K. Das, and B. S. Patro "Prospects of 2D Junctionless Channel Transistor (JLCT) towards Analog and RF metrics using Si and SiGe in Device layer", Journal of Low Power Electronics, Vol. 13, No 3, pp. 1-9, September 2017. (American Scientific Publisher)
B Vandana, J K Das, B S Patro, S K Mohapatra, "Physical insight of junctionless transistor with simulation study of Strained channel.". ECTI Transactions on Electrical Engineering, Electronics, and Communications, vol. 15, no. 01, pp.1-7, 2017. (ECTI)
B Vandana, J K Das, B S Patro, S K Mohapatra, “Exploration Towards Electrostatic Integrity For SiGe On Insulator (SG-OI) On Junctionless Channel Transistor (JLCT).”, Facta Universitatis, Series: Electronics and Energetics, vol. 30, no. 3, pp. 383-390. 2017. (Facta Universitatis)
Shiva Prasad Das, Ananya Dastidar, Partha Sarkar, S. K. Mohapatra, “Mixed Mode Performance of GaAs UTB-MOSFET With Extra Insulator Region And Undoped Buried Oxide Region”, Facta Universitatis, Series: Electronics and Energetics, vol. 30, no. 3, pp. 375-382. 2017. (Facta Universitatis)

Conferences

Trupti Mayee Behera, S. K. Mohapatra, Proshikshya Mukjerjee, and Harish Kumar Sahoo. "Work-In-Progress: DEEC-VD: A Hybrid Energy Utilization Cluster-Based Routing Protocol for WSN for Application in IoT." In 2017 International Conference on Information Technology (ICIT), pp. 97-100. IEEE, 2017.
B Vandana, J K Das,S K Mohapatraand B K Kaushik, “Effectiveness of High Permittivity Spacer for Underlap regions of Wavy-Junctionless FinFET at 22 nm node and Scaling Short Channel Effects”, 21^st International Symposium on VLSI Design and Test (VDAT 2017) , IIT Roorkee, INDIA, 29^th Jun-2^nd July, 2017.
S. P. Nayak, P. Dutta, S. K. Mohapatra, "Improvement of transconductance and gate source capacitance of Al0.27Ga0.73N/GaN HEMT at 45nm gate length with In0.1Ga0.9N back-barrier," 2017 Devices for Integrated Circuit (DevIC), Kalyani, India, pp. 131-135, 2017.
B Vandana, J K Das,S K Mohapatraand M Sumathi Jyothi, “Impact on Gate Oxide material of Inverted ‘T’ Junctionless FinFET at 22 nm Technology node”, International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech 2017) , Science City, Kolkata, Apr.28-29, 2017.
Prabhupada Samal, Veera Venkata Subrahmanya, Kumar Bhajana, S. K. Mohapatra, “Structural Analysis of 1.1kV 4H-SiC Power DMOSFETs and it’s Susceptibility to high Temperature”, International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech 2017) , Science City, Kolkata, Apr.28-29, 2017.
Soumya Prava Nayak, Pradipta Dutta, S. K. Mohapatra, “Performance Enhancement in Al0.3Ga0.7N/GaN HEMT based inverter using MOSHEMT”, International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech 2017) , Science City, Kolkata, Apr.28-29, 2017.

2016

Conferences

Vandana B, B S Patro, J K Das, S K Mohapatra, “SiGe on Insulator (SG-OI) on Junctionless Channel Transistor (JLCT): A new device for scaling with improved switching action”, 2nd International Conference on Micro-electronics, Communication and Computation-2016, SanDiego, USA, Sep., 2016.
S. K. Mohanty, S. Sengupta, S. K. Mohapatra, “Test bench automation to overcome verification challenge of SOC Interconnect”, 2015 International Conference on Man and Machine Interfacing (MAMI). IEEE, Bhubaneswar, Apr., 2016.

2015

Journals

S. K. Mohapatra, K. P. Pradhan, D. Singh, and P. K. Sahu, “The Role of Geometry Parameters and Fin Aspect Ratio of sub-20nm SOI-FinFET: An Analysis towards Analog and RF Circuit Design”, IEEE Transactions on Nanotechnology, vol. 14, no. 3, pp. 546 - 554, 2015. (IEEE)
K. P. Pradhan, P. K. Sahu, D. Singh, L. Artola, and S. K. Mohapatra, “Reliability analysis of charge plasma based double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET”, Superlattices and Microstructures, vol. 85, pp. 149-155, 2015. (Elsevier)
K. P. Pradhan, S. K. Mohapatra, and P. K. Sahu, “Impact of Channel and Metal Gate Work Function on GS-DG MOSFET: A Linearity Analysis”, ECS J. Solid State Sci. Technol., vol. 9, no. 9, pp. 393-397, 2015. (ECS)
K. P. Pradhan, S. K. Mohapatra, P. K. Sahu, “Design Equivalent Scaling on Double Gate FinFET towards Analog & RF FOMs: A TCAD Estimation”, Journal of Low Power Electronics, Vol. 11, no. 3, pp. 316-322, 2015. (American Scientific Publisher)
P. K. Sahu, S. K. Mohapatra, and K. P. Pradhan, “Zero temperature-coefficient bias point over wide range of temperatures for single-and double-gate UTB-SOI n-MOSFETs with trapped charges”, Materials Science in Semiconductor Processing, vol. 31, pp. 175-183, 2015. (Elsevier)
S. K. Mohapatra, K. P. Pradhan, L. Artola, and P. K. Sahu, “Estimation of Analog/RF FOMs using Device Design Engineering in GS-DG-MOSFET”, Materials Science in Semiconductor Processing, vol. 31, pp. 455-462, 2015. (Elsevier)
S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Temperature dependence inflection point in Ultra-Thin Si directly on Insulator (SDOI) MOSFETs: An influence to key performance metrics”, Superlattices and Microstructures, vol. 78, pp. 134-143, 2015. (Elsevier)
K. P. Pradhan, M. R. Kumar, S. K. Mohapatra, P. K. Sahu, “Analytical modeling of threshold voltage for Cylindrical Gate All Around (CGAA) MOSFET using center potential”, Ain Shams Engineering Journal, vol. 6, pp. 1171-1177, 2015. (Elsevier)
B Jena, K P Pradhan, S Dash, G P Mishra, P K Sahu and S K Mohapatra, “Performance analysis of undoped cylindrical gate all around (GAA) MOSFET at subthreshold regime”, Advances in Natural Sciences: Nanoscience and Nanotechnology, vol. 6, pp. 1-4, 2015. (IOP Science)
S K Mohapatra, K P Pradhan, P K Sahu, S Parija. "Impact of Strain on Fully Depleted Strained Gate Stack Double Gate MOSFET: A Simulation Study." ECTI Transactions on Electrical Engineering, Electronics, and Communications, vol.13, no.2 , pp. 54-57, 2015. (ECTI)
B Jena, K P Pradhan, P K Sahu, S Dash, G P Mishra, S K Mohapatra, “Investigation on Cylindrical Gate All Around (GAA) to Nanowire MOSFET for Circuit Application”, Facta Universitatis, Series: Electronics and Energetics, vol. 28, no. 4, pp. 637-643, 2015. (Facta Universitatis)
S. K. Mohapatra, K. P. Pradhan, G. S. Pati, and P. K. Sahu, “Relative appraisal of Ultra-Thin Body MOSFETs: An analytical modeling including hot carrier induced degradation," Informacije Midem-Journal of Microelectronics Electronic Components and Materials, vol. 45, pp. 57-65, 2015. (MIDEM Society)
S. K. Mohapatra, K. P. Pradhan, P. K. Sahu, “ZTC bias point of advanced fin based device: The importance and exploration”, Facta Universitatis, Series: Electronics and Energetics, vol. 28, no. 3, 2015. (Facta Universitatis)

Conferences

K. P. Pradhan, D. Singh, S. K. Mohapatra, P. K Sahu, “Double Material Gate Oxide (DMGO) SiGe-on-Insulator (SGOI) MOSFET: A proposal and analysis”, IEEE Electron Devices and Solid-State Circuits (EDSSC), Singapore, June, 2015.
K. P. Pradhan, D Singh, S K Mohapatra, P K Sahu, “Assessment of III-V FinFETs at 20 nm node: A Process variation analysis”, International Conference on Recent Trends in Computing (ICRTC), Delhi, March, 2015.
D Singh, K. P. Pradhan, S K Mohapatra, P K Sahu, “Optimization of Underlap Length for DGMOSFET and FinFET”, International Conference on Recent Trends in Computing (ICRTC), Delhi, March, 2015.
D. Singh, S. Panda, S. K. Mohapatra, K. P. Pradhan, P. K. Sahu, “Performance Analysis of UTB-DG MOSFET over SG MOSFET”, International Conference on Micro-electronics and Communication and Computation, San Diego, USA, Feb. 2015.

2014

Journals

K. P. Pradhan, S. K. Mohapatra, P. K. Sahu, and D. K. Behera, “Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET”, Microelectronics Journal, vol. 45, no. 2, pp. 144-151, 2014. (Elsevier)
S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Improved Performance in GS-DG-MOSFET with Dual Material Gate and Lateral Asymmetric Channel”, Int. J. of Nano and Biomaterials, vol. 5, no. 4, 2014. (Inderscience)
P. K. Sahu, S. K. Mohapatra, and K. P. Pradhan, “Impact of Down-scaling on Analog/RF Performance of sub-100nm GS-DG MOSFET”, Informacije Midem-Journal of Microelectronics Electronic Components and Materials, vol. 44, no. 2, pp. 119-125, Mar. 2014. (MIDEM Society)
S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Resolving the bias point for wide range of temperature applications in high-k/metal gate nanoscale DG-MOSFET”, Facta Universitatis, Series: Electronics and Energetics, vol. 27, no. 4, pp. 613-619, Dec. 2014. (Facta Universitatis)
S. K. Mohapatra, K. P. Pradhan, P. K. Sahu, G. S. Pati, and M. R. Kumar, “The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study”, Advances in Natural Sciences: Nanoscience and Nanotechnology, vol. 5, no. 4, pp. 1-7, Nov. 2014. (IOP Science)
S. K. Mohapatra, K. P. Pradhan, P. K. Sahu, and M. R. Kumar, “The performance measure of GS-DG MOSFET: an impact of metal gate work function”, Advances in Natural Sciences: Nanoscience and Nanotechnology, vol. 5, no. 2, pp. 1-6, Mar. 2014. (IOP Science).
P. K. Sahu, K. P. Pradhan, and S. K. Mohapatra, “A Study on SCEs of FD-S-SOI MOSFET in Nanoscale”, Universal Journal of Electrical and Electronic Engineering, vol. 2, no. 1, pp. 37-43, 2014.
M. R. Kumar, S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “A Simple Analytical Center Potential Model for Cylindrical Gate All Around (CGAA) MOSFET”, Journal of Electron Devices, vol. 19, pp. 1648-1653, Mar. 2014. (JelDev)
S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Influence of High-k Gate Dielectric on Nanoscale DG-MOSFET”, International Journal of Advanced Science & Technology, vol. 65, 2014. (Science and Engineering Research and Society)

Conferences

S. K. Mohapatra, K. P. Pradhan, P. K. Sahu, D. Singh, and S. Panda, “Ultra-Thin Si Directly on Insulator (SDOI) MOSFETs at 20 nm gate length”, IEEE International Conference on High-Performance Computing and Applications, Bhubaneswar, Odisha, India, Dec. 2014.
D. Singh, S. Panda, S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Static performance analysis on UTB-SG and DG MOSFETs with Si and III-V channel materials”, IEEE International Conference on High-Performance Computing and Applications, Bhubaneswar, Odisha, India, Dec. 2014.
D. Singh, S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Variation study of process parameters in Trigate SOI-FinFET”, IEEE INDICON, Emerging Trends and Innovation in Technology, Pune, India, Dec. 2014.
S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Linearity and Analog Performance Analysis in GSDG-MOSFET with Gate and Channel Engineering”, IEEE INDICON, Emerging Trends and Innovation in Technology, Pune, India, Dec. 2014.
S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Improved Performance in GS-DG-MOSFET with Dual Material Gate and Lateral Asymmetric Channel," International Conference on Automatic Control, Modelling & Simulation, Brasov, Romania, Jun. 2014.

2013

Journals

P. K. Sahu, S. K. Mohapatra, and K. P. Pradhan, “A Study of SCEs and Analog FOMs in GS-DG-MOSFET with Lateral Asymmetric Channel Doping”, Journal of Semiconductor Technology and Science, vol. 13, no. 6, pp. 647-654, Dec. 2013. (IEIE, Korea)
K. P. Pradhan, S. K. Mohapatra, P. K. Agarwal, P. K. Sahu, D. K. Behera, and J. Mishra, “Symmetric DG-MOSFET with gate and channel engineering: A 2-D simulation study”, Microelectronics and Solid State Electronics, vol. 2, no. 1, pp. 1-9, Feb. 2013. (Scientific & Academic Publishing, USA)
S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Some Device De-sign Considerations to Enhance the Performance of DG-MOSFETs”, Transactions on Electrical And Electronic Materials, vol. 14, no. 6, pp. 291-294, Dec. 2013. (Korean Institute of Electrical and Electronic Material Engineers)
K. P. Pradhan, P. K. Agarwal, P. K. Sahu, and S. K. Mohapatra, “Role of High-k Materials in Nanoscale TM-DG MOSFET: A Simulation Study”, Invertis Journal of Science and Technology, vol. 6, no. 4, pp. 1-5, 2013.

Conferences

K. P. Pradhan, P. K. Agarwal, P. K. Sahu, and S. K. Mohapatra, “Role of high-k materials in Nanoscale TM-DG MOSFET: A simulation study”, National Conference on Recent Developments in Electronics, New Delhi, India, Jan. 2013.

2012

Journals

S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Nanoscale SOI N-MOSFETS with different gate engineering having biaxial strained channel-a superlative study”, Journal of Electron Devices, vol. 15, pp. 1261-1268, Sep. 2012. (JelDev)
S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Investigation of Prefabrication Models of Double Gate MOSFETs in Nanoscale for High-Performance Circuit Application”, Nano Trends: A Journal of Nanotechnology and Its Applications, vol. 13, pp. 40-44, Oct. 2012. (Nano Science and Technology Consortium)

Conferences

S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “A new nanoscale DG MOSFET design with enhanced performance a comparative study”, Signal Processing and Information Technology, Springer Publishing, Dubai, Dec., 2012.
P. K. Agarwal, K. P. Pradhan, S. K. Mohapatra, and P. K. Sahu, “Insulating layer parameters are still in reduction of kink”, IEEE Nirma University International Conference on Engineering, Ahmedabad, Dec. 2012.
K. P. Pradhan, P. K. Agarwal, S. K. Mohapatra, and P. K. Sahu, “The impact of high-k gate dielectric materials over short channel parameters on sub-100 nm MOSFET”, National Seminar on Ferroelectrics & Dielectrics, Bhubaneswar, India, Dec. 2012.
S. K. Mohapatra, K. P. Pradhan, and P. K. Sahu, “Effect of channel & gate engineering on Double Gate (DG) MOSFET-A comparative study”, IEEE International Conference on Emerging Electronics, Bombay, India, Dec. 2012.
K. P. Pradhan, S. K. Mohapatra, and P. K. Sahu, “An analytical surface potential and threshold voltage model of fully depleted strained-SOI MOSFETs in nanoscale with high-k gate oxide”, IEEE International Conference on Emerging Technology Trends in Electronics, Communication, and Networking, Surat, Gujarat, India, Dec., 2012.

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