[1] G.-H. Buh, “Constitutional Amendment for Post-industrial Society”, Journal of Korea Technology Innovation Society, 21(3), 1179-1206 (2018).
[2] G.-H. Buh et al., "Integration of Sub-melt Laser Annealing on Metal Gate CMOS Devices for Sub 50 nm Node DRAM", IEDM Tech. Digest., pp.863-866 (2006)
[3] G.-H. Buh et al., "Interface states as an active component for 20 nm gate-length planar MOSFET with electrostatic channel extension (ESCE)", IEDM Tech. Digest., pp.832-835 (2005).
[1] G.-H. Buh et al., "Dynamics of resistance switching induced by charge carrier fluence", J. Appl. Phys. 108, 074101, (2010)
[2] Inrok Hwang et al., “Resistive switching transition induced by a voltage pulse in a Pt/NiO/Pt structure”, Appl. Phys. Lett. 97, 052106 (2010)
[3] G.-H. Buh et al., “Time-dependent electroforming in NiO resistive switching devices”, Appl. Phys. Lett. 95, 142101 (2009)
[4] Chan-Hyun Park, H. Chang, J-O Lee, G.-H. Buh and K-j Kong, “Multiscale Simulation of the Electronic Structure Variation of Carbon Nanotubes by Mechanical Deformations”, Journal of the Korean Physical Society, Vol. 55, No. 5, November (2009)
[5] E-K Jeonet al., “Resolving microscopic interfaces in Si1−xGex alloy nanowire devices”, Nanotechnology 20 (2009) 115708
[6] G.-H. Buh et al., “Coulomb interaction among transporting charge carriers confined in two dimensions”, J. Appl. Phys. 104, 083716 (2008)
[7] G.-H. Buh et al., “On-Chip Electrical Breakdown of Metallic Nanotubes for Mass Fabrication of Carbon-Nanotube-Based Electronic Devices”, IEEE Trans. Nanotechnol., vol. 7, No 5, pp.624 – 627(2008)
[8] D.-H. Lee et al., "Improved Cell Performance for Sub-50 nm DRAM with Manufacturable Bulk FinFET Structure", IEEE VLSI (2007)
[9] G.-H. Buh et al., "Integration of Sub-melt Laser Annealing on Metal Gate CMOS Devices for Sub 50 nm Node DRAM", IEDM Tech. Digest., pp.863-866 (2006)
[10] G-H Yon et al.,(corresponding), "Ultrashallow junction formation using plasma doping and laser annealing for sub-65 nm technology nodes", Jpn. J. Appl. Phys. Vol. 45, No. 4B, pp. 2961-2964 (2006)
[11]. G.-H. Buh et al., "Quantitative Analysis of Ultra-shallow Junction of Sub 50 nm Gate-length Transistors: Junction Depth, Sheet Resistance, Short Channel Effect, and Transistor Performance", J. Vac. Sci. Technol. B 24, 503 (2006)
[12] G.-H. Buh et al., "Dopant Loss of Ultra-Shallow Junction by Wet Chemical Cleaning", J. Vac. Sci. Technol. B 24, 499 (2006)
[13] S. Heo et al., "Ultrashallow Arsenic n+/p Junction Formed by AsH3 Plasma Doping", Jpn. J. Appl. Phys. Vol. 45, No. 13, pp. L373-L375 (2006)
[14] D. Lee et al., "Electrical Characteristics of Ultra-Shallow p+/n Junction Formed by BF3 Plasma Doping and Two Step Annealing Process", Electrochem. Solid-State Lett. 9, G121 (2006)
[15] D. Lee et al., "Ultra-Shallow p+/n Junction Prepared by Low Energy BF3 Plasma Doping and KrF Excimer Laser Annealing", Electrochem. Solid-State Lett. 9, G19 (2006)
[16] G.-H. Buh et al., "Interface states as an active component for 20 nm gate-length planar MOSFET with electrostatic channel extension (ESCE)", IEDM Tech. Digest., pp.832-835 (2005).
[17] G.-H. Buh et al., "Quantification of Shallow-junction Dopant Loss during CMOS Process", AIP Conf. Proc. 788, 275 (2005)
[18] J. W. Lee et al., (corresponding) "Elimination of Surface State Induced Edge Transistors in High Voltage NMOSFETs for Flash Memory Devices", Microelectronics Reliability, 45, 1394-1397(2005)
[19] S. Hyun et al., (corresponding) "Ultrathin gate oxide with a reduced transition layer grown by plasma-assisted oxidation", Appl. Phys. Lett., Vol. 85, No. 6, pp. 988-990 (2004)
[20] G. Birdwell et al., "Excitonic transitions in b-FeSi2 epitaxial films and single crystals", J. Appl. Phys., Vol. 95, No. 5, pp. 2441-2446 (2004)
[21] G.-H. Buh, Chi Tran, and J. J. Kopanski, "PSPICE analysis of a scanning capacitance microscope sensor", J. Vac. Sci. Technol. B, Vol. 22, No.1 pp. 417-422 (2004)
[22] G.-H. Buh and J. J. Kopanski, "Atomic force microscope laser illumination effects on a sample and its application for transient spectroscopy", Appl. Phys. Lett., 83, pp. 2486-2488 (2003)
[23]. G.-H. Buh et al., "Factors influencing the capacitance-voltage characteristics measured by the scanning capacitance microscope", J. Appl. Phys., 94, pp. 2680-2685 (2003)
[24] G.-H. Buh et al., "Electrical characterization of an operating Si pn-junction diode with scanning capacitance microscopy and Kelvin probe force microscopy", J. Appl. Phys., 90, pp. 443-448 (2001)
[25] G.-H. Buh, H. J. Chung, and Y. Kuk, "Real-time evolution of trapped charge in a SiO2 layer: An electrostatic force microscopy study", Appl. Phys. Lett., Vol. 79, pp. 2010-2012 (2001)
[26] G.-H. Buh et al., "Imaging of a silicon pn junction under applied bias with scanning capacitance microscopy and Kelvin probe force microscopy", Appl. Phys. Lett., 77, pp. 106-108 (2000)
[27] C. J. Kang, G.-H. Buh, S. Lee, C. K. Kim, K. M. Mang, C. Im, and Y. Kuk, "Charge trap dynamics in a SiO2 layer on Si by scanning capacitance microscopy", Appl. Phys. Lett., Vol. 74, No.13, pp. 1815-1817 (1999)
[28] J. Y Park, Jared D. Lera, H. J. Choi, G.-H. Buh, C. J. Kang, J. H. Jung, S. S. Choi, D. Jeon, and Young Kuk, "Characterization of two by two electron-beam microcolumn array aligned with field emission array", J. Vac. Sci. Technol. B, Vol. 16, No.2, pp. 826-828 (1998)
[29] Se-Jong Kahng, J. Y. Park, G.-H. Buh, J. Lee, Y. Khang, and Y. Kuk, "Effect of atomic hydrogen on the growth of Ge/Si(100)", J. Vac. Sci. Technol. A, Vol. 15, No.3, pp. 927-929 (1997)
[30] Y. Khang, K. M. Mang, G.-H. Buh, and Y. Kuk, "Schottky barrier height measurement on NiSi2/Si(100) by capacitance microscope", J. Vac. Sci. Technol. B, Vol. 14, No.2, pp. 1221-1223 (1996)
뉴사피엔스 챗GPT (공동저작)
979-11-982224-3-5 (2023.03.30.)
KAIST 미래를 말하다(공동저작)
979-11-93205-11-2(2023.10.20.)
시그널 코리아 2024 (공동저작)
979-11-93205-13-6 (2023.11.15)
• 부경호, 김병건, “문재인 정부의 혁신지향 공공조달 방안: 정책적 함의와 역할” 한국기술혁신학회 추계 학술대회,(2021)
• 부경호, “포스트-산업화 시대의 과학·기술과 헌법” 기술혁신학회지, 21(3), 1179-1206 (2018)
• 부경호, 8명의 과학기술자, 그리고 실리콘밸리의 탄생. 과학기술정책, 27(9), 44-51.(2017)
• 부경호. “국가 R&D 성과의 귀속·활용 제도의 고찰 및 개선 방향”. 한국기술혁신학회 학술대회 논문집, pp. 1191 - 1205 (2017)
• 부경호 “실리콘밸리 탄생 60주년: 그 혁신 기술과 주역들”, 물리학과첨단기술, 한국물리학회(2017.09)
• 부경호, Global IP Trend 2015, 한국지식재산연구원(2015), ISSUE 06 : “지식재산 거래” ISSN pp. 2233-5676
• 부경호, “지식재산 거래시장 활성화”, IP Focus, 한국지식재산연구원(2015.12.) [이슈페이퍼]
• 부경호 et al., (초청강연) “우리 기술시장의 정책적 동인: 실패의 궤적과 그 치유”, 한국기술혁신학회 학술대회, 35-54. (2015)
• 부경호 et al., 지식재산 관점의 반도체 산업 동향 및 진단 ch.1,2 & 8 (ISBN:978-89-6199-628-0 13500)
• 부경호 “50 나노 실리콘 반도체 기술의 현황”, 물리학과첨단기술, 한국물리학회(2007.04)
G.-H. Buh., Reflective structure and reflective photo mask, KR 10-2482229(2022.12.23.)
G.-H. Buh et al., An Industrial Facility Operating Device Based on Standard Operation Level Evaluations and a Method for Operating It(2022.03.14.)
G.-H. Buh et al., Methods of forming semiconductor device, KR 10-1172853(2012.08.03.) & US 7351622(2008.04.01.)
Plasma doping technology and its application for next-generation 3D transistors: FinFET and GAA*
* GAA(Gate-all-round) is a transistor structure that Samsung has strategically adopted to outperform its competitors at 3nm and beyond.
G.-H. Buh et al., Semiconductor device including carrier accumulation layers, KR 10-1133212(2012.03.28.) & US 7514744(2009.04.07.)
G.-H. Buh et al., Method for producing carbon nanotube transistor and carbon nanotube transistor thereby,, KR 10-0930997 (2009.12.02.)
G.-H. Buh et al., NAND-type flash memory devices including selection transistors with an anti-punchthrough impurity region and methods of fabricating the same, KR 10-0854498(2008.08.20.) & US 7783421(2010.03.23.)
G.-H. Buh et al., Semiconductor transistors having surface insulation layers and methods of fabricating such transistors, KR 10-0719365(2007.05.11.) & US 7492006(2009.02.17.)
G.-H. Buh et al., Methods of forming integrated circuit memory devices having a charge storing layer formed by plasma doping, KR 10-0683854(2007.02.09.)
G.-H. Buh et al., High-voltage transistor of semiconductor device and method of forming the same, KR 10-0614658(2006.08.14.)
G.-H. Buh et al., Method of increasing a free carrier concentration in a semiconductor substrate, KR 10-0541052(2005.12.28.), US 7485554(2009.02.03.) & US 7176049(2007.02.13.)