Embedded Files
You need to run DDR3 calibration for a new DDR3 layout and I also run it in case I use different memory chips (different manufacturer or different size).
1) Download DDR_Stress_Tester_V1.0.2.zip or check this post for latest version
*Note: If you are a developer, you may want to have a look at Mx6DQSDL DDR3 Script Aid V0.08.xlsx from this forum to get DDR3 register values for different memory chips.
2) Connect iMX6 Rex micro USB (J21) to your Windows computer. If your module is completely new, JP2 must not be fitted. If you have already programmed efuses, JP2 must be fitted. The USB series resistors must be in positions: R62 Fitted / R65 Fitted / R63 Not Fitted / R67 Not Fitted.
3) Go to “DDR_Stress_Tester_V1.0.2\Binary\scripts\MX6_series_boards\SabreSD\RevC_and_RevB\MX6DQ\” and update “MX6Q_SabreSD_DDR3_register_programming_aid_v1.5.inc” according to your DDR3 settings. For the very first time, you can just use the default file.
4) Turn ON the iMX6 Rex board. Go to “DDR_Stress_Tester_V1.0.2\Binary\” and run:
W:\WORK\FEDEVEL\iMX6 Rex Module\V1I1\Software\DDR_Stress_Tester_V1.0.2\Binary>DDR_Stress_Tester.exe -t mx6x -df scripts\MX6_series_boards\SabreSD\RevC_and_RevB\MX6DQ\MX6Q_SabreSD_DDR3_register_programming_aid_v1.5.inc
5) Follow the instructions. It may look like this:
W:\WORK\FEDEVEL\iMX6 Rex Module\V1I1\Software\DDR_Stress_Tester_V1.0.2\Binary>DD
R_Stress_Tester.exe -t mx6x -df scripts\MX6_series_boards\SabreSD\RevC_and_RevB\
MX6DQ\MX6Q_iMX6Rex_2GB_DDR3_register_programming_aid_v1.5.inc
MX6DQ opened.
HAB_TYPE: DEVELOP
Image loading...
download Image to IRAM OK
Re-open MX6x device.
Running DDR test..., press "ESC" key to exit.
******************************
DDR Stress Test (1.0.2) for MX6DQ
Build: Dec 10 2013, 12:31:54
Freescale Semiconductor, Inc.
******************************
=======DDR configuration==========
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 2048MB
==================================
What ARM core speed would you like to run?
Type 0 for 650MHz, 1 for 800MHz, 2 for 1GHz, 3 for 1.2GHz
ARM set to 1GHz
Please select the DDR density per chip select (in bytes) on the board
Type 0 for 2GB; 1 for 1GB; 2 for 512MB; 3 for 256MB; 4 for 128MB; 5 for 64MB; 6
for 32MB
For maximum supported density (4GB), we can only access up to 3.75GB. Type 9 to
select this
DDR density selected (MB): 2048
Calibration will run at DDR frequency 528MHz. Type 'y' to continue.
If you want to run at other DDR frequency. Type 'n'
DDR Freq: 528 MHz
Would you like to run the write leveling calibration? (y/n)
Please enter the MR1 value on the initilization script
This will be re-programmed into MR1 after write leveling calibration
Enter as a 4-digit HEX value, example 0004, then hit enter
0004 You have entered: 0x0004
Start write leveling calibration
Write leveling calibration completed
MMDC_MPWLDECTRL0 ch0 after write level cal: 0x0012001F
MMDC_MPWLDECTRL1 ch0 after write level cal: 0x00230011
MMDC_MPWLDECTRL0 ch1 after write level cal: 0x0017001F
MMDC_MPWLDECTRL1 ch1 after write level cal: 0x000E001D
Would you like to run the DQS gating, read/write delay calibration? (y/n)
Starting DQS gating calibration...
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BYTE 0:
Start: HC=0x01 ABS=0x60
End: HC=0x04 ABS=0x2C
Mean: HC=0x03 ABS=0x06
End-0.5*tCK: HC=0x03 ABS=0x2C
Final: HC=0x03 ABS=0x2C
BYTE 1:
Start: HC=0x01 ABS=0x60
End: HC=0x04 ABS=0x2C
Mean: HC=0x03 ABS=0x06
End-0.5*tCK: HC=0x03 ABS=0x2C
Final: HC=0x03 ABS=0x2C
BYTE 2:
Start: HC=0x01 ABS=0x54
End: HC=0x04 ABS=0x28
Mean: HC=0x02 ABS=0x7D
End-0.5*tCK: HC=0x03 ABS=0x28
Final: HC=0x03 ABS=0x28
BYTE 3:
Start: HC=0x01 ABS=0x4C
End: HC=0x04 ABS=0x24
Mean: HC=0x02 ABS=0x77
End-0.5*tCK: HC=0x03 ABS=0x24
Final: HC=0x03 ABS=0x24
BYTE 4:
Start: HC=0x01 ABS=0x68
End: HC=0x04 ABS=0x3C
Mean: HC=0x03 ABS=0x12
End-0.5*tCK: HC=0x03 ABS=0x3C
Final: HC=0x03 ABS=0x3C
BYTE 5:
Start: HC=0x01 ABS=0x60
End: HC=0x04 ABS=0x2C
Mean: HC=0x03 ABS=0x06
End-0.5*tCK: HC=0x03 ABS=0x2C
Final: HC=0x03 ABS=0x2C
BYTE 6:
Start: HC=0x01 ABS=0x28
End: HC=0x03 ABS=0x68
Mean: HC=0x02 ABS=0x48
End-0.5*tCK: HC=0x02 ABS=0x68
Final: HC=0x02 ABS=0x68
BYTE 7:
Start: HC=0x01 ABS=0x4C
End: HC=0x04 ABS=0x20
Mean: HC=0x02 ABS=0x75
End-0.5*tCK: HC=0x03 ABS=0x20
Final: HC=0x03 ABS=0x20
DQS calibration MMDC0 MPDGCTRL0 = 0x432C032C, MPDGCTRL1 = 0x03240328
DQS calibration MMDC1 MPDGCTRL0 = 0x432C033C, MPDGCTRL1 = 0x03200268
Note: Array result[] holds the DRAM test result of each byte.
0: test pass. 1: test fail
4 bits respresent the result of 1 byte.
result 00000001:byte 0 fail.
result 00000011:byte 0, 1 fail.
Starting Read calibration...
ABS_OFFSET=0x00000000 result[00]=0x11111111
ABS_OFFSET=0x04040404 result[01]=0x11111111
ABS_OFFSET=0x08080808 result[02]=0x11111111
ABS_OFFSET=0x0C0C0C0C result[03]=0x11011011
ABS_OFFSET=0x10101010 result[04]=0x00011001
ABS_OFFSET=0x14141414 result[05]=0x00011000
ABS_OFFSET=0x18181818 result[06]=0x00010000
ABS_OFFSET=0x1C1C1C1C result[07]=0x00000000
ABS_OFFSET=0x20202020 result[08]=0x00000000
ABS_OFFSET=0x24242424 result[09]=0x00000000
ABS_OFFSET=0x28282828 result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
ABS_OFFSET=0x30303030 result[0C]=0x00000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00100000
ABS_OFFSET=0x50505050 result[14]=0x00100000
ABS_OFFSET=0x54545454 result[15]=0x00100100
ABS_OFFSET=0x58585858 result[16]=0x01100111
ABS_OFFSET=0x5C5C5C5C result[17]=0x11100111
ABS_OFFSET=0x60606060 result[18]=0x11111111
ABS_OFFSET=0x64646464 result[19]=0x11111111
ABS_OFFSET=0x68686868 result[1A]=0x11111111
ABS_OFFSET=0x6C6C6C6C result[1B]=0x11111111
ABS_OFFSET=0x70707070 result[1C]=0x11111111
ABS_OFFSET=0x74747474 result[1D]=0x11111111
ABS_OFFSET=0x78787878 result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
MMDC0 MPRDDLCTL = 0x3A2E3234, MMDC1 MPRDDLCTL = 0x34322A3C
Starting Write calibration...
ABS_OFFSET=0x00000000 result[00]=0x11111111
ABS_OFFSET=0x04040404 result[01]=0x10111111
ABS_OFFSET=0x08080808 result[02]=0x10100011
ABS_OFFSET=0x0C0C0C0C result[03]=0x10100011
ABS_OFFSET=0x10101010 result[04]=0x10100010
ABS_OFFSET=0x14141414 result[05]=0x00100010
ABS_OFFSET=0x18181818 result[06]=0x00000000
ABS_OFFSET=0x1C1C1C1C result[07]=0x00000000
ABS_OFFSET=0x20202020 result[08]=0x00000000
ABS_OFFSET=0x24242424 result[09]=0x00000000
ABS_OFFSET=0x28282828 result[0A]=0x00000000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x00000000
ABS_OFFSET=0x30303030 result[0C]=0x00000000
ABS_OFFSET=0x34343434 result[0D]=0x00000000
ABS_OFFSET=0x38383838 result[0E]=0x00000000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x00000000
ABS_OFFSET=0x40404040 result[10]=0x00000000
ABS_OFFSET=0x44444444 result[11]=0x00000000
ABS_OFFSET=0x48484848 result[12]=0x00000000
ABS_OFFSET=0x4C4C4C4C result[13]=0x00000000
ABS_OFFSET=0x50505050 result[14]=0x00000000
ABS_OFFSET=0x54545454 result[15]=0x00000000
ABS_OFFSET=0x58585858 result[16]=0x00000000
ABS_OFFSET=0x5C5C5C5C result[17]=0x00000000
ABS_OFFSET=0x60606060 result[18]=0x00000000
ABS_OFFSET=0x64646464 result[19]=0x00000000
ABS_OFFSET=0x68686868 result[1A]=0x01000000
ABS_OFFSET=0x6C6C6C6C result[1B]=0x01010000
ABS_OFFSET=0x70707070 result[1C]=0x01010000
ABS_OFFSET=0x74747474 result[1D]=0x01111110
ABS_OFFSET=0x78787878 result[1E]=0x11111111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x11111111
MMDC0 MPWRDLCTL = 0x3C3C4442,MMDC1 MPWRDLCTL = 0x44344438
MMDC registers updated from calibration
Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x432C032C
MPDGCTRL1 PHY0 (0x021b0840) = 0x03240328
MPDGCTRL0 PHY1 (0x021b483c) = 0x432C033C
MPDGCTRL1 PHY1 (0x021b4840) = 0x03200268
Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x3A2E3234
MPRDDLCTL PHY1 (0x021b4848) = 0x34322A3C
Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x3C3C4442
MPWRDLCTL PHY1 (0x021b4850) = 0x44344438
The DDR stress test can run with an incrementing frequency or at a static freq
To run at a static freq, simply set the start freq and end freq to the same valu
e
Would you like to run the DDR Stress Test (y/n)?
^C
W:\WORK\FEDEVEL\iMX6 Rex Module\V1I1\Software\DDR_Stress_Tester_V1.0.2\Binary>
5) These sections from the calibration are important:
...
Write leveling calibration completed
MMDC_MPWLDECTRL0 ch0 after write level cal: 0x0012001F
MMDC_MPWLDECTRL1 ch0 after write level cal: 0x00230011
MMDC_MPWLDECTRL0 ch1 after write level cal: 0x0017001F
MMDC_MPWLDECTRL1 ch1 after write level cal: 0x000E001D
...
MMDC registers updated from calibration
Read DQS Gating calibration
MPDGCTRL0 PHY0 (0x021b083c) = 0x432C032C
MPDGCTRL1 PHY0 (0x021b0840) = 0x03240328
MPDGCTRL0 PHY1 (0x021b483c) = 0x432C033C
MPDGCTRL1 PHY1 (0x021b4840) = 0x03200268
Read calibration
MPRDDLCTL PHY0 (0x021b0848) = 0x3A2E3234
MPRDDLCTL PHY1 (0x021b4848) = 0x34322A3C
Write calibration
MPWRDLCTL PHY0 (0x021b0850) = 0x3C3C4442
MPWRDLCTL PHY1 (0x021b4850) = 0x44344438
Open “MX6Q_SabreSD_DDR3_register_programming_aid_v1.5.in” and update following section (replace the numbers based on the calibration results)
// write leveling, based on Freescale board layout and T topology
// For target board, may need to run write leveling calibration
// to fine tune these settings
// If target board does not use T topology, then these registers
// should either be cleared or write leveling calibration can be run
setmem /32 0x021b080c = 0x0012001F
setmem /32 0x021b0810 = 0x00230011
setmem /32 0x021b480c = 0x0017001F
setmem /32 0x021b4810 = 0x000E001D
//######################################################
//calibration values based on calibration compare of 0x00ffff00:
//Note, these calibration values are based on Freescale's board
//May need to run calibration on target board to fine tune these
//######################################################
//Read DQS Gating calibration
setmem /32 0x021b083c = 0x432C032C // MPDGCTRL0 PHY0
setmem /32 0x021b0840 = 0x03240328 // MPDGCTRL1 PHY0
setmem /32 0x021b483c = 0x432C033C // MPDGCTRL0 PHY1
setmem /32 0x021b4840 = 0x03200268 // MPDGCTRL1 PHY1
//Read calibration
setmem /32 0x021b0848 = 0x3A2E3234 // MPRDDLCTL PHY0
setmem /32 0x021b4848 = 0x34322A3C // MPRDDLCTL PHY1
//Write calibration
setmem /32 0x021b0850 = 0x3C3C4442 // MPWRDLCTL PHY0
setmem /32 0x021b4850 = 0x42344438 // MPWRDLCTL PHY1
6) Go back to the point 3) and run the calibration again. Do it for couple of times on couple of boards. When you will be getting similar numbers, go to 7)
7) Update your u-boot. Open the u-boot file with memory configuration settings:
gedit imx6rex-u-boot-2009.08/board/freescale/mx6q_rex/flash_header.S
Find this code and update it (use the numbers from calibration):
#else /* i.MX6Q */
dcd_hdr: .word 0x40a002D2 /* Tag=0xD2, Len=83*8 + 4 + 4, Ver=0x40 */
write_dcd_cmd: .word 0x049c02CC /* Tag=0xCC, Len=83*8 + 4, Param=0x04 */
/* DCD */
//corrected to 2GB MT41K256M16HA-125:E based on Sabre AI
MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x798, 0x000C0000)
MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x758, 0x00000000)
MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x588, 0x00000030)
MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x594, 0x00000030)
MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x56c, 0x00000030)
MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x578, 0x00000030)
MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030)
MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00000030)
MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x58c, 0x00000000)
MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x59c, 0x00000030)
MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x5a0, 0x00000030)
MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x78c, 0x00000030)
MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x750, 0x00020000)
MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x5a8, 0x00000028)
MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x5b0, 0x00000028)
MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x524, 0x00000028)
MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x51c, 0x00000028)
MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x518, 0x00000028)
MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x50c, 0x00000028)
MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x5b8, 0x00000028)
MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x5c0, 0x00000028)
MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x774, 0x00020000)
MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x784, 0x00000028)
MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x788, 0x00000028)
MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x794, 0x00000028)
MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x79c, 0x00000028)
MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x7a0, 0x00000028)
MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x7a4, 0x00000028)
MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x7a8, 0x00000028)
MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x748, 0x00000028)
MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x5ac, 0x00000028)
MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x5b4, 0x00000028)
MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x528, 0x00000028)
MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x520, 0x00000028)
MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x514, 0x00000028)
MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x510, 0x00000028)
MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x5bc, 0x00000028)
MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x5c4, 0x00000028)
MXC_DCD_ITEM(39, MMDC_P0_BASE_ADDR + 0x800, 0xA1390003)
# write leveling
MXC_DCD_ITEM(40, MMDC_P0_BASE_ADDR + 0x80c, 0x0013001F) //Updated for iMX6 Rex V1I1, original = 0x001F001F, 1GB 0x00190023
MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x810, 0x00230011) //Updated for iMX6 Rex V1I1, original = 0x001F001F, 1GB 0x00260019
MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x80c, 0x0017001F) //Updated for iMX6 Rex V1I1, original = 0x001F001F, 1GB 0x0017001D
MXC_DCD_ITEM(43, MMDC_P1_BASE_ADDR + 0x810, 0x000E001D) //Updated for iMX6 Rex V1I1, original = 0x001F001F, 1GB 0x000C001F
# DQS gating, read delay, write delay calibration values
MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x83c, 0x432C0328) //Updated for iMX6 Rex V1I1, original = 0x4333033F, 1GB 0x43280328
MXC_DCD_ITEM(45, MMDC_P0_BASE_ADDR + 0x840, 0x03240328) //Updated for iMX6 Rex V1I1, original = 0x032C031D, 1GB 0x02460318
MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x83C, 0x432C033C) //Updated for iMX6 Rex V1I1, original = 0x43200332, 1GB 0x432C0338
MXC_DCD_ITEM(47, MMDC_P1_BASE_ADDR + 0x840, 0x03200268) //Updated for iMX6 Rex V1I1, original = 0x031A026A, 1GB 0x03280268
MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x848, 0x3A2E3234) //Updated for iMX6 Rex V1I1, original = 0x4D464746, 1GB 0x362E3034
MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x848, 0x34322A3A) //Updated for iMX6 Rex V1I1, original = 0x47453F4D, 1GB 0x30322E3A
MXC_DCD_ITEM(50, MMDC_P0_BASE_ADDR + 0x850, 0x3C3C4242) //Updated for iMX6 Rex V1I1, original = 0x3E434440, 1GB 0x403C4642
MXC_DCD_ITEM(51, MMDC_P1_BASE_ADDR + 0x850, 0x4836483C) //Updated for iMX6 Rex V1I1, original = 0x47384839, 1GB 0x4836483C
MXC_DCD_ITEM(52, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333)
MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x820, 0x33333333)
MXC_DCD_ITEM(54, MMDC_P0_BASE_ADDR + 0x824, 0x33333333)
MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x828, 0x33333333)
MXC_DCD_ITEM(56, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333)
MXC_DCD_ITEM(57, MMDC_P1_BASE_ADDR + 0x820, 0x33333333)
MXC_DCD_ITEM(58, MMDC_P1_BASE_ADDR + 0x824, 0x33333333)
MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x828, 0x33333333)
MXC_DCD_ITEM(60, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800)
MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800)
//MDC init
MXC_DCD_ITEM(62, MMDC_P0_BASE_ADDR + 0x004, 0x00020036)
MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x008, 0x09444040)
MXC_DCD_ITEM(64, MMDC_P0_BASE_ADDR + 0x00c, 0x8A8F7955)
MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x010, 0xFF328F64)
MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x014, 0x01FF00DB)
MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x018, 0x00001740)
MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000)
MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x02c, 0x000026D2)
MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x030, 0x008F1023)
MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x040, 0x00000047)
MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x000, 0x841A0000)
MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x01c, 0x04088032)
MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033)
MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x01c, 0x00048031)
MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x09408030)
MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040)
MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x020, 0x00005800)
MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x818, 0x00011117)
MXC_DCD_ITEM(80, MMDC_P1_BASE_ADDR + 0x818, 0x00011117)
MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x004, 0x00025576)
MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x404, 0x00011006)
MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000)
#endif
In case you are changing also memory size, you need to update config file
# cd
# sudo gedit ltib/rpm/BUILD/imx6rex-u-boot-2009.08/include/configs/mx6q_rex.h
and tell u-boot about the new size (search for “DRAM”):
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR
#define PHYS_SDRAM_1_SIZE (1u * 512 * 1024 * 1024) //512MB DDR
//#define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024) //1GB DDR
//#define PHYS_SDRAM_1_SIZE (2u * 1024 * 1024 * 1024) //2GB DDR
#define iomem_valid_addr(addr, size) \
(addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
8) Compile the new uboot
# cd /home/fedevel/ltib/rpm/BUILD/imx6rex-u-boot-2009.08/
# ./build_u-boot.sh
# sudo cp u-boot.bin /tftp/
9) Boot your module into u-boot and update the u-boot on your module:
> mw.b 0x10800000 0xFF 0x80000;tftp 0x10800000 u-boot.bin;sf probe 3:2;sf erase 0x0 0x80000;sf write 0x10800000 0x0 0x80000
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