Speakers

Bio: With a strong background in FPGA chip development, cryptography, and high-performance computing, Ben combines technical expertise with entrepreneurial leadership.

Technical Session

Leveraging FPGAs and RISC Architectures for Full Data Transparency and Secure Virtualization

In the FPGA development and RISC design context, this talk will center around leveraging FPGAs and RISC Architectures for Full Data Transparency and Secure Virtualization, including: demonstrating how FPGAs, built on RISC architecture principles, can offer true transparency in data processing; exploring the ability to run multiple isolated instances of operating systems on a single FPGA platform, and highlighting the advantages for critical infrastructure, secure computing, and next-generation data centers.

Workshop

Qsentinal Hands-on workshop

See the workshop description here.

Bio: Emeritus Chair of the Linux Professional Institute, Master of Science, Computer Science Rensselaer Polytechnic Institute.

Keynote

The opposite of "Free" is "Lack of Control"

Many people have a problem understanding "Free Software". How can something that is "Free" be any good?   How can developing "Free Software" be sustainable?  In Portuguese "Software Libre" seems much clearer, yet there are still some doubts.   This talk will explain how Free Software has existed from before Closed Source Software, refute some of the myths around Free Software and extend the model to "Open Hardware" and "Free Data".

Workshop

Qsentinal Hands-on workshop

See the workshop description here.

Technical Session

Project Cauã: Ready to Go: What, When and Why

Technical Session

Project Cauã: Ready to Go: Who and How

Bio: Roman Shaposhnik is a co-founder of ZEDEDA. Prior to ZEDEDA, Roman helped to build scalable, cloud-native compute and data platforms at Sun microsystems, Pivotal, and Cloudera. 

Technical Session

Democratizing inference of open-weight models on RISC-V many-core accelerators

Workshop

AI Plumbers

The AI Plumbers Conference (AIPIC) is where the real work of plumbing the depths of the AI ecosystem happens. It is not a flashy keynote-driven event—it is a hands-on, technically intense gathering focused on solving the integration and coordination problems that arise between different subsystems that have to work together in order to produce that final inference answer for your AI agents. From the specialized GPU/NPU/TPU/APU chips through system libraries that provide software abstractions for massively parallel hardware capabilities and all the way to compute kernels, compilers, inference frameworks and agentic networks “user space”. It is where we get the folks who really know their code and their silicon into one room to hash out the hard stuff.

What makes AIPC different is that it’s not just another conference with slides and spectators. It’s where you come to talk about the things that are NOT working well between layers of the stack. Are Tenstorrent hardware and compute kernel changes making life harder for eusable and extensible compiler infrastructure (MLIR) or ggml/tinygrad? Is a new hardware enablement strategy going to cause regressions upstream? These are the kinds of discussions that benefit from in-person participation from people who are actually writing and maintaining these components. Above all, we need people who are trying to build end-to-end AI inference products (think racks!) out of all these moving parts (and going completely insane at the ever shifting landscape).

If you're working on any of the hardware acceleration AI chips or inference frameworks or any of the tightly coupled layers above, you should absolutely come. We need your input, your patches, and maybe even your complaints—because fixing real problems starts with showing up and speaking up. AIPC is where long-standing design disagreements get resolved, where new ideas get buy-in, and where we all leave a little less grumpy and a lot more aligned. So bring your patches, your questions, and your flameproof keyboard—we'll see you there.