These projects will be presented during the technical sessions: Session 1: System Design and Architecture, Session 2: System Level Electrical Test. The call is open, interested ones may write to the SRA leads. The project should align to the SRAs objective. The list is only of those which are being submitted and reviewed till today.
System Design and Architecture: Problems
Design for High Performance Execution of Different Workloads
IP Integration for Efficient System Design
System Simulation Methodology & Emulation
Technique Development
System Design and Architecture: Projects
Scalable 3D chiplet interconnect
Next generation interconnect pathways
Energy efficient edge computing
Secure compute engines for edge inference
In-Memory AI accelerators
Heterogeneous SoC for robotic computing
Hardware Accelerator for SCNN
System-on-Chip for real-time image analysis
System Level Electrical Test: Problems
Chiplet SiP test
System level testing
Yield enhancement and test data analytics
Turn-around time and efficiency improvement
Analog test efficiency
System Level Electrical Test: Projects
3D Chiplet DFT
Multi accelerator parallel testing
Low-power ATPG algorithm and design
Secure stream scan architecture
System-level testing of 3D Interconnect
DPPM reduction via functional testing
Software based processor testing
Multi-EDT scan chain diagnosis using AI
Analog and mixed signal fault modelling