Energy Efficient Loop Acceleration on Coarse-Grained Reconfigurable Array (CGRA) ARCHITECTURES

With the increasing demand for high performance computing in application domains with stringent power budgets, Coarse-Grained Reconfigurable Array (CGRA) architectures have proven to be good targets as specialised hardware in low-power embedded applications, such as wireless sensor networks (WSN), internet of things (IoT) and cyber physical systems (CPS). Due to the regular structure with several highly optimized processing elements (PEs) and simple interconnects, CGRAs provide high performance and energy efficiency. For most of the applications that are run on the CGRA, a major portion of the computation time and energy is spent on loops. Since loops are the hot spots, research on CGRA is naturally focused on optimizing loop execution. In this work, we address low-power loop acceleration, focusing on architectural and programming model features of CGRAs.