PUBLICATIONS

 Journals: 

1. S. Rathore, R. K. Jaisawal, P. N. Kondekar, and N. Bagga, "Demonstration of a Nanosheet FET with High Thermal Conductivity Material as Buried Oxide: Mitigation of Self-Heating Effect," IEEE Transactions on Electron Devices, Feb. 2023

2. S. Rathore, R. K. Jaisawal, P.N.Kondekar, and N. Bagga, "Trap and self-heating effect-based reliability analysis to reveal early aging effect in nanosheet FET," vol. 200, pp. 108546, Solid-State Electronics, Dec. 2022.

3. R. K. Jaisawal, S. Rathore, P.N. Kondekar, and N. Bagga, "Reliability of TCAD study for HfO2-doped Negative capacitance FinFET with different Material-Specific dopants," Solid-State Electronics, vol. 199, pp. 108531, Nov. 2022.

4. T. Santra, A. Dixit, R. K. Jaisawal, S.Rathore, S. Sarkhel, and N. Bagga, "Investigation of Geometrical Impact on a P+ Buried Negative Capacitance SOI FET," Microelectronics Journal, Oct. 2022.

5. S. Rathore, R. K. Jaisawal, N. Gandhi, P.N. Kondekar, and N. Bagga, "Substrate BOX engineering to mitigate the self-heating induced degradation in nanosheet transistor," Microelectronics Journal, vol. 129, pp. 105590, Sept. 2022.

6. R. K. Jaisawal, S. Rathore, N. Gandhi, P. N. Kondekar, and Navjeet Bagga, "Role of Temperature on Linearity and Analog/RF Performance Merits of a Negative Capacitance FinFET," Semiconductor Science and Technology, vol. 37, pp. 115003, Sept. 2022.

7. V. Chauhan, D. P. Samajdar, and N. Bagga, “Exploration and Device Optimization of Dielectric-Ferroelectric Sidewall Spacer in Negative Capacitance FinFET,” IEEE Transaction on Electron Devices, Early Access, July 2022, doi: 10.1109/TED.2022.3186272.

8. S. Rathore, R. K. Jaisawal, P. N. Kondekar, and N. Bagga, “Design Optimization of Three-Stacked Nanosheet FET from Self-Heating Effects Perspective, IEEE Transactions on Device and Materials Reliability, Early Access, June 2022, doi: 10.1109/TDMR.2022.3181672.

9. V. Chauhan, D. P. Samajdar, and N. Bagga, “Demonstration of Improved Short Channel Performance Metrics for Ferroelectric Concentric Negative Capacitance FinFET,” Silicon Springer, June 2022, doi: https://doi.org/10.1007/s12633-022-01993-0.

10. V. Chauhan, D. P. Samajdar, and N. Bagga, “Quasi-analytical model of surface potential and drain current for Trigate negative capacitance FinFET: a superposition approach,” Semi. Sci. Tech., Jul. 2022.

11. R. K. Jaisawal, S. Rathore, P. N Kondekar, S. Yadav, B. Awadhiya, P. Upadhyay and N. Bagga, "Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques," Semiconductor Science and Technology, March. 2022.

12. N. Jain, I. Mal, D P Samajdar, and N. Bagga, “Theoretical Exploration of the Optoelectronic Properties of InAsNBi/InAs heterostructures for Infrared Applications: A Multi-Band k.p Approach,” Materials Science in Semiconductor Processing, vol. 148, pp. 106822, April 2022, doi: https://doi.org/10.1016/j.mssp.2022.106822.

13. A. Dixit, D. P. Samajdar and N. Bagga, “Demonstration of Geometrical Impact of Nanowire on GaAs1-xSbx Transistor Performance,” IEEE Transaction on Electron Devices, Dec. 2021.

14. N. Chauhan, N. Bagga, S. Banchhor, C. Garg, A. Sharma, A. Datta, S. Dasgupta and A. Bulusu, "BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: an analog perspective," Nanotechnology IOP Science, Oct. 2021.

15. N. Chauhan, N. Bagga, S. Banchhor, A. Datta, S. Dasgupta, and B. Anand, “Negative to Positive Differential Resistance Transition in Ferroelectric FET: Physical Insight and Utilization in Analog Circuits,” IEEE Transactions on Ultrasonic, Ferroelectrics and Frequency control, Sept. 2021

16. A. Dixit, D. P. Samajdar and N. Bagga, “Impact of the mole fraction modulation on the RF/DC performance of GaAs1-xSbx FinFET,” Int. Jour. of Numerical Modelling, Electronic Devices and Fields, Sept. 2021.

17. V. Chauhan, D. P. Samajdar, N. Bagga and A. Dixit, "A Novel Negative Capacitance FinFET with Ferroelectric Spacer: Proposal and Investigation," IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, Early Access, Jul. 2021.

18. A.Dixit, D.P.Samajdar, and N. Bagga, "Dielectric Modulated GaAs1-xSbX FinFET as a Label-Free Biosensor: Device Proposal and Investigation," Semiconductor Science and Technology, IOP Science, Early Access, Jun. 2021.

19. A. Dixit, D. P. Samajdar, N. Bagga, D. S. Yadav, "Performance investigation of a novel GaAs1-xSbx-on-insulator (GASOI) FinFET: Role of interface trap charges and hetero dielectric," vol. 26, Materials Today Communications, Mar. 2021.

20. N. Bagga, N. Chauhan, S. Banchhor, D. Gupta and S. Dasgupta, “Demonstration of a Novel Tunnel FET with Channel Sandwiched by Drain,” Semi. Sci. and Tech. IOP, vol. 35, Nov. 2019.

21. N. Bagga, N. Chauhan, D. Gupta and S. Dasgupta, “A Novel Twofold Tunnel FET with Reduced Miller Capacitance: Proposal and Investigation,” IEEE Transactions on Electron Devices, vol. 66, no. 7, pp. 3202-3208, Jul. 2019.

22. N. Bagga, Anil Kumar and S. Dasgupta, “Demonstration of a Novel Two Source Region Tunnel FET,” IEEE Transactions on Electron Devices, vol. 64, issue 12, pp. 5256-5262, Oct. 2017.

23. N. Bagga and S. Dasgupta, “Surface Potential and Drain Current Analytical Model of Gate All Around Triple Metal TFET, IEEE Trans. Electron Devices , vol. 64, issue 2, pp. 606 – 613, 2017.

24. N. Bagga, Anil Kumar, A. Bhattacharjee and S. Dasgupta, “Performance evaluation of a novel GAA Schottky Junction TFET with heavily doped pocket, Superlattices and Microstructures, 2017.

25. S. Sarkhel, N. Bagga and S. K. Sarkar, “A compact analytical model of binary metal alloy silicon-on-nothing (BMASON) tunnel FET with interface trapped charges,” Journal of Computational Electronics, doi: 10.1007/s10825-017-1030-7, pp. 1-10, 2017.

26. N. Bagga, Saheli Sarkhel and S. K. Sarkar, “Exploring the Asymmetric Characteristics of a Double Gate MOSFET with Linearly Graded Binary Metal Alloy Gate Electrode for Enhanced Performance,” IETE Journal of Research, vol. 62, no. 6, pp. 786-794, 2016.

27. S. Sarkhel, N. Bagga and S. K. Sarkar, “Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor,” Journal of Computational Electronics, vol. 15, no. 1, pp. 104–114, 2016.

28. N. Bagga and S. K. Sarkar, “An Analytical Model for Tunnel Barrier Modulation in Triple Metal Double Gate TFET, IEEE Trans. Electron Devices, vol. 62, no. 7, pp. 2136 – 2142, 2015.

 Conferences: 

1. S. Banchhor, N. Bagga, N. Chauhan, S. Manikandan, A. Dasgupta, S. Dasgupta, and A. Bulusu, "A New Insight into the Saturation Phenomenon in Nanosheet Transistor: A Device Optimization Perspective," IEEE Electron Device Technology and Manufacturing Conference (EDTM'23), Seoul, Korea, 2023

2. N. Gandhi, R. K. Jaisawal, S. Rathore, P. N. Kondekar, S. Banchhor, and N. Bagga, "Demonstration of a Junctionless Negative Capacitance FinFET-based Hydrogen Gas Sensor: A Reliability Perspective," IEEE Electron Device Technology and Manufacturing Conference (EDTM'23), Seoul, Korea, 2023

3. J. Patel, N. Aggarwal, N. Bagga, and S. Dasgupta, "Small-Signal Model of Nanosheet FET for High-Frequency Range: A Design Perspective of Parallel Stacking and Dual-Dielectric Spacer," IEEE Electron Device Technology and Manufacturing Conference (EDTM'23), Seoul, Korea, 2023

4. R. K. Jaisawal, S.Rathore, N. Gandhi, P. N. Kondekar, S. Banchhor, V B. Sreenivas, Y. S. Song, and N. Bagga, "Self-Heating and Interface Traps Assisted Early Aging Revelation and Reliability Analysis of Negative Capacitance FinFET, " IEEE Electron Device Technology and Manufacturing Conference (EDTM'23), Seoul, Korea, 2023

5. S. Rathore, R. K. Jaisawal, P. N. Kondekar, N. Gandhi, S. Banchhor, Y. S. Song, and N. Bagga, "Self-Heating Aware Threshold Voltage Modulation Conforming to Process and Ambient Temperature Variation for Reliable Nanosheet FET," IEEE International Reliability Physics Symposium (IRPS), California, USA, March 2023

6. S. Rathore, R. K. Jaisawal, P. N. Kondekar, and N. Bagga, "Device Design Aware and Interface Thermal Resistance Assisted Self-Heating Analysis in Nanosheet FET," IEEE ICEE 2022, Bangalore, India. (BEST Paper)

7. R. K. Jaisawal, S. Rathore, P. N. Kondekar, and N. Bagga, "Role of Interfacial Oxide on Capacitance Matching in a Negative Capacitance FinFET: A Reliability Perspective," IEEE ICEE 2022, Bangalore, India.

8. J. Patel, N. Bagga, S. Banchhor, and S. Dasgupta, "Symmetric/Asymmetric Spacer Optimization for Multi Fin FinFET: Analog Perspective for High-Frequency Operation," IEEE ICEE 2022, Bangalore, India.

9. M. Subramaniyan, N. Chauhan, N. Bagga, A. Kumar, S. Banchhor, S. Roy, A. Dasgupta, A. Bulusu, and S. Dasgupta, "Analysis and Modeling of Leakage Currents in Stacked Gate-All-Around Nanosheet Transistors," IEEE ICEE 2022, Bangalore, India.

10. R. K. Jaisawal, S. Rathore, P. N. Kondekar, and N. Bagga, “Reliability of TCAD Study for HfO2-doped Negative Capacitance FinFET with Different Material Specific Dopants, SISPAD’22, Granada Spain, September 2022

11. S. Rathore, R. K. Jaisawal, P. N. Kondekar, and N. Bagga, “Trap and Self-Heating Effect Based Reliability Analysis to Reveal Early Aging Effect in Nanosheet FET,” SISPAD’22, Granada Spain, September 2022

12. Navjeet Bagga, Kai Ni, Nitanshu Chauhan, Om Prakash, Sharon Hu and Hussam Amrouch, "Cleaved-Gate Ferroelectric FET for Reliable Multi-Level Cell Storage," In Proceedings of the IEEE 60th International Reliability Physics Symposium (IRPS’22), Dallas, U.S., 2022.

13. N. Chauhan, C. Garg, Kai Ni, A. Behera, S. Yadav, S. Banchhor, N. Bagga, A. Dasgupta, A. Datta, S. Dasgupta, A. Bulusu, "Impact of Random Spatial Fluctuation in Non-Uniform Crystalline Phases on Multidomain MFIM Capacitor and Negative Capacitance FDSOI," In Proceedings of the IEEE 60th International Reliability Physics Symposium (IRPS’22), Dallas, U.S., 2022.

14. R. K. Jaisawal, S. Rathore, P. N. Kondekar, and N. Bagga, “Impact of Temperature on NDR Characteristics of a Negative Capacitance FinFET: Role of Landau Parameter (alpha),” VDAT’22, Jammu, India, July-2022.

15. N. Chauhan, A. Gupta, G. Bajpai, N. Bagga, S. Banchhor, S. Dasgupta and A. Bulusu, “Unveiling the Impact of Interface Traps Induced on Negative Capacitance Nanosheet FET: A Reliability Perspective,” VDAT’22, Jammu, India, July-2022.

16. S. Banchhor, N. Bagga, N. Chauhan, S. Manikandan, A. Dasgupta, S. Roy, A. Bulusu and S. Dasgupta, "Analysis of Self-Heating in 5nm Stacked Nanosheet Transistor Applications, In Proceedings of XXI International Workshop on the Physics of Semiconductor Devices (IWPSD 2021), Dec. 2021.

17. V. Chauhan, D. P. Samajdar and N. Bagga, “Performance Investigation of Ferroelectric Spacers for Negative Capacitance FinFETs,” Proc. of Int. Symp. On Materials of the Millennium: Emerging Trends and Future Prospects, 2021.

18. N. Jain, I. Mal, D. Samajdar and N. Bagga, “Investigation of Optical and Electronic Properties of InAsNBi for Infrared Detection,” Proc. of Int. Symp. On Materials of the Millennium: Emerging Trends and Future Prospects, 2021.

19. A. Dixit, D. P. Samajdar and N. Bagga, “Label-Free Biosensing using Dielectric Modulated GaAs1-xSbx FinFET under Dry/Wet Environment, in Proc. IEEE INDICON, Dec. 2021.

20. A. Dixit, D. P. Samajdar and N. Bagga, “GaAs1-xSbx Label-Free Biosensor using Trigate and Gate-all-around FET,” in Proc. IEEE IBSSC, Nov. 2021.

21. S. Sarkhel, R. R. Dey, S. Das, S. Sarkar, T. Santra, and N. Bagga, “A Novel Dual Metal Double Gate Grooved Trench MOS Transistor: Proposal and Investigation,” in Proc. Springer COMSYS, Oct. 2021.

22. A. Dixit, D. P. Samajdar and N. Bagga, "Performance Evolution of the GaAs1-xSbx FinFET for the Mole Fraction Variation," IEEE DeviC Conference, May 2021.

23. A. Gupta, G. Bajpai, P. Singhal, N. Bagga, Om Prakash, S. Banchhor, H. Amrouch, and N. Chauhan, "Traps Based Reliability Barrier on Performance and Revealing Early Ageing in Negative Capacitance (NC) FET," Proc. IEEE IRPS, March 2021.

24. A. Dixit, D.P. Samajdar, V. Chauhan and N. Bagga, “Performance Comparison of III-V and Silicon FinFETs for Ultra-Low Power VLSI Applications,” Proc. IEEE CCSN, 2020 (Best Paper)

25. S Sarkhel, and N Bagga, "Analytical Model of a Strain Induced Lateral Channel Workfunction Engineered Surrounding Gate MOSFET," Proc. IEEE ASPCON, 2020.

26. N. Chauhan, G. Bajpai, S. Banchhor, and N. Bagga, "Analysis of Transient Negative Capacitance Characteristics for Stabilization and Amplification," 24th International Symposium on VLSI Design and Test (VDAT), Jul. 2020.

27. N. Bagga, N. Chauhan, A. Bulusu and S. Dasgupta, “Demonstration of Novel Ferroelectric-Dielectric Tunnel FET, IEEE Proc. of MOS-AK, 2019.

28. N. Bagga and S. Dasgupta, “Demonstration of Novel Structures for Improvement in Performance of Tunnel FETs,” Ph.D. Forum at VLSI Design Conference, 2019.

29. N. Chauhan, N. Bagga, S. Banchhor, S. Dasgupta and A. Bulusu, “Simulation Study of Transient Negative Capacitance with Stabilization and Amplification,” Proc. IWPSD, 2019.

30. D. Gupta, N. Bagga and S. Dasgupta, “Reduced Gate Capacitance of Dual Metal Double Gate over Single Metal Double Gate Tunnel FET: A Comparative Study,” Proc. IEEE ICEDSS, 2018.

31. N. Bagga and S. Dasgupta, “Analytical Threshold Voltage Model of Gate All Around Triple Metal Tunnel FET,” Proc. IEEE of ICEDSS, pp. 146-149, Mar. 2017.

32. N. Bagga, Anil Kumar and S. Dasgupta, “SOI Based Double Source Tunnel FET (DS-TFET) with High On-Current and Reduced Turn-on Voltage,” Proc. IEEE of MIEL, Serbia, Europe, 2017. (BEST Paper)

33. N. Bagga, Saheli Sarkhel and S. K. Sarkar, “Analytical Model for ID-VD characteristics of a Triple Metal Double Gate TFET,” Proc. IEEE ICCCA, 2016.

34. N. Bagga, S. Sarkhel and S. K. Sarkar, “Recent Research Trends in Gate Engineered Tunnel FET for Improved Current Behavior by subduing the Ambipolar Effects: A Review,” Proc. IEEE ICCCA, 2015.

35. P. K. Dutta, Navjeet Bagga, K. Naskar and S. K. Sarkar, “Analysis and Simulation of Dual Metal Double Gate SON MOSFET using Hafnium Dioxide for Better Performance,” Proc. of IET, 2015.

36. Saheli Sarkhel, Navjeet Bagga and S. K. Sarkar, " Analytical Modeling and Simulation of Work function Engineered Gate Junction-less high-k dielectric Double Gate MOSFET: A Comparative Study," Proc. of IET, 2015.

 Journals: 

1. Tianchen Wang, Sandeep Kumar Samal, Sung Kyu Lim, and Yiyu Shi, “Entropy Production Based Full-Chip Fatigue Analysis: From Theory to Mobile Applications”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 38, No. 1, pp 84-95, January 2019.

2. Tiantao Lu, Caleb Serafy, Zhiyuan Yang, Sandeep Kumar Samal, Sung Kyu Lim, and Ankur Srivastava, “TSV-based 3D ICs: Design Methods and Tools”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Keynote Paper, Vol. 36, No. 10, pp 1593-1619, October 2017.

3. Shreepad Panth, Sandeep Kumar Samal, Kambiz Samadi, Yang Du, and Sung Kyu Lim, “Tier Degradation of Monolithic 3D ICs: A Power Performance Study at Different Technology Nodes”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol 36, No. 8, pp. 1265-1273, August 2017.

4. Sandeep Kumar Samal, GuoQing Chen, and Sung Kyu Lim, “Improving Performance Under Process and Voltage Variations in Near-Threshold Computing Using 3D ICs”, ACM Journal of Emerging Technologies in Computing (JETC), Vol. 13, No. 4, Article 59, June 2017.

5. Sandeep Kumar Samal, Kambiz Samadi, Pratyush Kamal, Yang Du, and Sung Kyu Lim, “Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3D ICs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, No. 6, pp. 992-1003, June 2017.

6. Sandeep Kumar Samal, GuoQing Chen, and Sung Kyu Lim, “Machine Learning Based Variation Modeling and Optimization for 3D ICs”, Journal of Information and Communication Convergence Engineering (JICCE), Vol. 14, No. 4, pp. 258-267, 2016.

7. Sandeep Kumar Samal, Shreepad Panth, Kambiz Samadi, Mehdi Saeidi, Yang Du, and Sung Kyu Lim, “Adaptive Regression-based Thermal Modeling and Optimization for Monolithic 3D ICs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No. 10, pp. 1707-1720, October 2016.

8. Sandeep Kumar Samal, Yarui Peng, Mohit Pathak, and Sung Kyu Lim, “Ultralow-Power Circuit Design with Subthreshold/Near-Threshold 3D IC Technologies”, IEEE Transactions on Components, Packaging and Manufacturing Technology (TCPMT), Vol. 5, No. 7, pp. 980-990, July 2015.

9. Shreepad Panth, Sandeep Kumar Samal, Yun Seop Yu and Sung Kyu Lim, “Design Challenges and Solutions for Ultra-High-Density Monolithic 3D ICs”, Journal of Information and Communication Convergence Engineering (JICCE), Vol. 12, No. 3, pp. 186-192, 2014.

 Conferences: 

1. Sandeep Kumar Samal and Ritochit Chakraborty, “Interconnect Layout Automation with Modular Metal-Stacks for Foundry Manufacturing Process Optimization” IEEE International Conference on Circuits and Systems (ICCSS), 2026.

2. Ritochit Chakraborty, Sandeep Kumar Samal, Mangesh Kushare, Jingrong Zhou, and Ashok Murugavel, “Full-chip Layout Automation for Modular Metal-Stack to Enable Process and Yield Optimization” in Intel Design and Test Technology Conference, 2024

3. Bon Woong Ku, Yu Liu, Yingyezhe Jin, Sandeep Kumar Samal, Peng Li, and Sung Kyu Lim, “Design and Architectural Co-optimization of Monolithic 3D Liquid State Machine-based Neuromorphic Processor”, ACM Design Automation Conference (DAC), 2018.

4. Sandeep Kumar Samal, Sourabh Khandelwal, Asif Islam Khan, Sayeef Salahuddin, Chenming Hu, and Sung Kyu Lim, “Full Chip Power Benefits with Negative Capacitance FETs”, IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2017.

5. Jiajun Shi, Deepak Nayak, Srinivasa Banna, Robert Fox, Srikanth Samavedam, Sandeep Kumar Samal and Sung Kyu Lim, “A 14nm Finfet Transistor-Level 3D Partitioning Design to Enable High- Performance and Low-Cost Monolithic 3D IC”, IEEE International Electron Devices Meeting (IEDM), 2016.

6. Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, and Sung Kyu Lim, “Tier Partitioning Strategy to Mitigate BEOL Degradation and Cost Issues in Monolithic 3D ICs”, IEEE International Conference on Computer-Aided Design (ICCAD), 2016.

7. Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, and Sung Kyu Lim, “Monolithic 3D IC vs. TSV-based 3D IC in 14nm FinFET Technology”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2016.

8. Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, and Sung Kyu Lim, “How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions”, IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2016.

9. Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, and Sung Kyu Lim, “Impact of Transistor Technology on Power Savings in Monolithic 3D ICs”, IEEE International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2016.

10. Tianchen Wang, Sandeep Kumar Samal, Sung Kyu Lim, and Yiyu Shi, “A Novel Entropy Production Based Full-Chip TSV Fatigue Analysis”, IEEE International Conference on Computer-Aided-Design (ICCAD), 2015.

11. Sandeep Kumar Samal, Yang Li, GuoQing Chen, and Sung Kyu Lim, “Improving Performance in Near- Threshold Circuits Using 3D IC Technology”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015.

12. Deepak Nayak, Srinivasa Banna, Sandeep Kumar Samal, and Sung Kyu Lim, “Power, Performance, and Cost Comparisons of Monolithic 3D ICs and TSV-based 3D ICs”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2015.

13. Sandeep Kumar Samal, Kambiz Samadi, Pratyush Kamal, Yang Du, and Sung Kyu Lim, “Full Chip Impact Study of Power Delivery Network Designs in Monolithic 3D ICs“, IEEE International Conference on Computer-Aided Design (ICCAD), 2014.

14. Shreepad Panth, Sandeep Kumar Samal, Yun Seop Yu, and Sung Kyu Lim, “Design Challenged and Solutions for Ultra-High-Density Monolithic 3D ICs”, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2014 (Invited Paper).

15. Sandeep Kumar Samal, Yarui Peng, and Sung Kyu Lim, “Design and Analysis of Ultra Low Power Processors Using Sub/Near-Threshold 3D Stacked ICs”, SRC TECHON Conference, 2014.

16. Sandeep Kumar Samal, Shreepad Panth, Kambiz Samadi, Mehdi Saeidi, Yang Du and Sung Kyu Lim, “Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs”, ACM Design Automation Conference (DAC) 2014.

17. Sandeep Kumar Samal, Kiyoung Kim, Youngchan Kim, Taesung Kim, Hyuk-Jae Lee, Taewhan Kim and Sung Kyu Lim, “Ultra Low Power 2-tier 3D Stacked Sub-threshold H.264 Intra Frame Encoder“, IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013.

18. Sandeep Kumar Samal, Yarui Peng, Yang Zhang and Sung Kyu Lim, “Design and Analysis of Ultra Low Power Processors Using Sub/Near-Threshold 3D Stacked ICs“, IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2013

 Book Chapters:

1. Sandeep Kumar Samal and Sung Kyu Lim, “Design and CAD Solutions for Cooling and Power Delivery for Monolithic 3D ICs”, in Handbook of 3D Integration, Vol 4: Design, Test and Thermal Management, edited by Paul Franzon et al, Wiley-VCH, 2019. (ISBN 978-3-5273-3855-9).

2. Sandeep Kumar Samal and Sung Kyu Lim, “Ultralow Power Processor Design with 3D IC Operating at Sub/Near-Threshold Voltages”, in CISS: Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting, edited by Chong-Min Kyung, Springer, 2015 (ISBN 978-94-017-9989-8).