Timeline]

[Jan.2024] Awarded with Best Paper award for the paper titled "Security Implications of Approximation: A Study of Trojan Attacks on Approximate Adders and Multipliers" at  37th IEEE International Conference on VLSI Design (VLSID) 2024.

[Oct. 2023] With the blessings of Mata Rani, my parents, and the guidance of my teachers, I am deeply grateful to have been honored with the prestigious Prime Minister's Research Fellowship.

[Oct. 2023] Our paper titled "Security Implications of Approximation: A Study of Trojan Attacks on Approximate Adders and Multipliers" has been selected to appear at the IEEE International Conference on VLSI Design (VLSID) 2024.

[Aug. 2023] Our paper titled "HyAdd: A Hybrid Approximate Adder for Energy-efficient Computing" has been accepted to appear at the 27th International Symposium on VLSI Design and Test (VDAT-2023). 

[Jul. 2023] Our journal, titled  "VADF: Versatile Approximate Data Formats for Energy-efficient Computing," has been accepted to appear at ACM Transactions on Embedded Computing Systems (ACM-TECS) 2023.

[Jun.2023] Our paper titled "CPU-DOCTOR: When an device's heart beat can be an acoustic side channel disassembler" has been accepted at Springer Journal of Cryptographic Engineering (JCEN) 2023.

[Feb. 2023] Our paper titled "VADF: Versatile Approximate Data Formats for Energy-efficient Computing" was accepted as a poster at the 60th ACM/IEEE Design Automation Conference (DAC) 2023.

[Jan. 2023] Our paper titled "Novel, Configurable Approximate Floating-point Multipliers for Error-Resilient Applications" was accepted at 24th International Symposium on Quality Electronic Design (ISQED-23), California, USA.

[Nov. 2022] Our paper titled "Aiding to Multimedia Accelerators: A Hardware Design for Efficient Rounding of Binary Floating Point Numbers" was accepted at Design, Automation, and Test in Europe Conference (DATE) 2023. 

[Oct. 2022] Our paper titled "DARK-Adders: Digital Hardware Trojan Attack on Block-Based Approximate Adders" was accepted at IEEE International Conference on VLSI Design (VLSID) 2023. 

[Aug.2022] Enrolled in Ph.D. program in Computer Science and Engineering. 

[Jul.2022] Earned B.Tech degree in ECE with 8.96 CGPA (Dept. Rank #2).

[Jul. 2022] Our journal titled "On the Performance and Optimization of HAPS Assisted Dual-Hop Hybrid RF/FSO Systems" was accepted at IEEE Access, early ACCESS  granted on 1 Aug. 2022.

[Jan. 2022] Our paper titled  "An Approximate Multiply-Accumulate Unit for Error-Tolerant Applications" was accepted in the IEEE International Symposium on Circuits and Systems (ISCAS) 2022.

 [Jan. 2022] Our paper titled "AxLEAP: Enabling Low Power Approximations Through Unified Power Format " was accepted in IEEE International Symposium on Circuits and Systems (ISCAS) 2022.

[Dec. 2021] Out paper titled "An Efficient Carry Speculative Approximate Adder with Rectification” was accepted at 23rd International Symposium on Quality Electronic Design (ISQED-22), California, USA.

[Dec. 2021] Our paper titled “HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications" was accepted at the 23rd International Symposium on Quality Electronic Design (ISQED-22), California, USA.

[Dec. 2021] Our paper titled "HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications" was awarded the best poster award at the HiPC 2021, Student Research Symposium (SRS).

[Nov. 2021] Our paper titled "HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications" was accepted at the HiPC 2021, Student Research Symposium (SRS) for a poster presentation.

[Jan. 2021] Our paper titled "SAM: a Segmentation Based Approximate Multiplier for Error Tolerant Applications" was accepted at ISCAS-2021.

[Sep. 2020] Our paper titled 'An Approximate Carry Estimating Simultaneous Adder with Rectification' was awarded the Best Paper Award [2nd place] at GLSVLSI 2020.

[Mar. 2020] Our paper titled 'An Approximate Carry Estimating Simultaneous Adder with Rectification' was accepted at GLSVLSI 2020.

[Dec. 2019] Our poster titled 'ACEP: An Accuracy-Configurable Carry Estimating Parallel Adder' was awarded the best poster award in the HiPC 2019, Student Research Symposium (SRS).

[Nov. 2019] Our poster titled 'ACEP: An Accuracy-Configurable Carry Estimating Parallel Adder' was accepted at the HiPC 2019, Student Research Symposium (SRS) for a poster presentation.

[Mar. 2019] I started reading research papers. This marks the beginning of my research career.

[Jul. 2018] Enrolled for B.Tech Program in Electronics and Communication Engineering.

[May 2017] Completed Class 12th with 91.4%

[May 2015]  Completed Class 10th  with 10 CGPA.

[Jun. 2006] Left my village "Diouni" situated in Smarer Block of Budaun district, Uttar Pradesh due to a lack of education faculties.