Dr. Jagadish D N - Research

Mobility of autonomous vehicles is a challenging task to implement. Under the given traffic circumstances, all agent vehicles behavior is to be understood and their paths for a short future needs to be predicted in order to decide upon the maneuver of the ego vehicle. We explore deep learning techniques to predict movement of agents in this work by implementing residual and conditional variational autoencoder deep learning networks. #AAAI2020 workshophttp://aium2021.felk.cvut.cz/papers/AI4UM_paper_4.pdf

Path prediction of autonomous vehicles is an essential requirement under any given traffic scenario. Trajectory of several agent vehicles in the vicinity of ego vehicle, at least for a short future, is needed to be predicted in order to decide upon the maneuver of the ego vehicle. We explore variational autoencoder networks to obtain multimodal trajectories of agent vehicles. In our work, we condition the network on past trajectories of agents and traffic scenes as well. The latent space representation of traffic scenes is achieved by using another variational autoencoder network. The performance of the proposed networks is compared against a residual baseline model. #PAKDD2021

Mobility of autonomous vehicles is a challenging task to implement. Under the given traffic circumstances, all agent vehicles’ behavior is to be understood and their paths for a short future needs to be predicted to decide upon the maneuver of the ego vehicle. We explore variational autoencoder networks to get multimodal predictions of agents. In our work, we condition the network on past trajectories of agents and traffic scenes as well. The latent space representation of traffic scenes is achieved by using another variational autoencoder network. The proposed networks are trained for varied prediction horizon. The performance of a network is compared with other networks trained on the dataset. #NeuralProcessingLetters2022

Multiple object detection using deep neural networks can lead to transportation vehicles estimate, a necessary requirement for prediction and management of road traffic and parking lot. Highly overlapped objects that look similar and objects that are there at far distances have lesser probability of detection by state-of-art techniques. We propose techniques to estimate the traffic at regions of poor detection probability in the image based on (i) density based clustering and (ii) exclusive object detection in the regions of poor detection. The proposed techniques lead to better estimation in comparison to state-of-art by approximately 12 %. We have utilized RetinaNet and YOLOv3 networks for object detection. #TENCON2020

Multiple vehicle detection using deep neural networks can lead to road traffic prediction, a necessary requirement for management of road traffic. Large area occlusion and vehicles that are there at far distances have lesser probability of detection by baseline object detection models. Neural network trained on vehicles data set detects multiple vehicles on road. We propose techniques to estimate traffic at regions of occlusion and poor detection probability in the video frame based on density based clustering. The estimated spatial-temporal traffic data is fed to a trained convolutional LSTM network to predict road traffic. #CVIP2020

In this work, a design technique for low energy consumption and area efficient successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. Digital-to-analogue conversion (DAC) equivalent voltage is acquired utilising passive sharing of charge between two unit capacitors and integration of the shared charge onto an input sampleand-hold capacitor, via a switched capacitor (SC) integrator circuit. The architecture is less parasitic sensitive and low noise, yielding an area and energy efficient ADC. To demonstrate the efficacy of the proposed technique, a ±350 mV 8 bit 0.78 MS/s ADC is designed in a 90 nm CMOS process. The ADC core has a small area footprint of 0.00145 mm^2 and has a figure-of-merit (FoM) of 11.39 fJ/conv-step. #IETCircuitsDevices&Systems2018

In this work, design technique and analysis of low energy consumption successive approximation register (SAR) analogue-to-digital converter (ADC) are presented. Despite the presence of parasitics, the dual capacitor array (CA) generates digital-to-analog (DAC) reference voltage with increased accuracy. The CA supports multiple parallel operations to enhance conversion speed. Unit sized capacitors in CAs are few in number and present good capacitance density, thereby providing area efficiency and ease of routing. A 9-bit SAR ADC using the proposed dual CA, implemented in a 90nm CMOS process, has a small core area footprint of 0.00371 mm^2 . At a 1 V supply and 100 KS/s, the ADC achieves an SNDR of 53.55 dB and consumes 0.47 µW, resulting in a figure of merit (FoM) of 14.5 fJ/conversion-step. #IETCircuitsDevices&Systems2018

Research interests: Machine learning, Neural networks and VLSI.