Publications

Prof. Subhendu K Sahoo (HoD EEE)

2022

1. Japa, Aditya, Subhendu K. Sahoo, Ramesh Vaddi, and Manoj Kumar Majumder. "Emerging tunnel FET and spintronics-based hardware-secure circuit design with ultra-low energy consumption." Journal of Computational Electronics (2022): 1-12.

2. Wagh, Mrunali D., Subhendu Kumar Sahoo, and Sanket Goel. "Laser-induced graphene ablated polymeric microfluidic device with interdigital electrodes for taste sensing application." Sensors and Actuators A: Physical 333 (2022): 113301.

3. Wagh, Mrunali D., Pavar Sai Kumar, Khairunnisa Amreen, Subhendu Kumar Sahoo, and Sanket Goel. "Integrated microfluidic device with MXene enhanced laser-induced graphene bioelectrode for sensitive and selective electroanalytical detection of dopamine." IEEE Sensors Journal 22, no. 14 (2022): 14620-14627.

4. Wagh, Mrunali D., S. B. Puneeth, Subhendu Kumar Sahoo, and Sanket Goel. "Wax-Printed Microfluidic Paper Analytical Device for Viscosity-Based Biosensing in a 3D Printed Image Analysis Platform." In Microactuators, Microsensors and Micromechanisms: MAMM 2022, pp. 301-309. Cham: Springer International Publishing, 2022

2021

1. Japa, Aditya., Majumder, M.K., Sahoo, S.K. and Vaddi, R., “Hardware Security exploiting post-CMOS Devices: Fundamental device characteristics, State-of-the-Art Countermeasures, Challenges and Roadmap”, in IEEE Circuits and Systems Magazine, vol. 21, no. 3, pp. 4-30, third quarter 2021, doi: 10.1109/MCAS.2021.3092532.

2. Apurva Kumari, S. K. Sahoo and M. C. Chinnaiah, "Fast and Efficient Visibility Restoration Technique for Single Image Dehazing and Defogging," in IEEE Access, vol. 9, pp. 48131-48146, 2021, doi: 10.1109/ACCESS.2021.3068446.

3.  Japa, Aditya., Majumder, M.K., Sahoo, S.K. and Vaddi, R., "Emerging Tunnel FET and Spintronics based Hardware Secure Circuit Design with Ultra-low Energy Consumption'' Accepted in Journal of Computational Electronics, Springer.

4. Japa, Aditya., Majumder, M.K., Sahoo, S.K. and Vaddi, R., “Tunnel FET based Ultra-Lightweight Reconfigurable TRNG and PUF Design for Resource Constrained Internet of Things”  International Journal of Circuit Theory and Applications. 2021 Aug;49(8):2299-311.

5.  Mrunali Wagh, Puneeth S B, Sanket Goel and Subhendu K Sahoo, “Development of Laser-Induced Graphene-based Automated Electro Microfluidic Viscometer for Biochemical Sensing Applications”  IEEE Transactions on Electron Devices, vol. 68(10), pp. 5184-5191, 2021

2020

1. Japa, Aditya, Manoj Kumar Majumder, Subhendu K. Sahoo, and Ramesh Vaddi. "Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage." International Journal of Circuit Theory and Applications 48, no. 4 (2020): 524-538

2. Kumar, Ganjikunta Ganesh, and Subhendu K. Sahoo. "Power-efficient compensation circuit for fixed-width multipliers." IET Circuits, Devices & Systems (2020).

3. Ganesh Kumar Ganjikunta; Subhendu Kumar Sahoo; “An Area and Power-Efficient Variable-Length Fast Fourier Transform for MR-OFDM Physical Layer of IEEE 802.15.4-g” IET Computers & Digital Techniques, vol. 14, no. 5, pp. 193-200, 9 2020, doi: 10.1049/iet-cdt.2018.5260.

4. Japa Aditya, Palagani Yellappa, Venkateswarlu Gonuguntla, Manoj Kumar Majumder, Subhendu K. Sahoo, Jun Rim Choi, and Ramesh Vaddi “A Low Voltage Discriminant Circuit for Pattern Recognition Exploiting the Asymmetrical Characteristics of Tunnel FET”, IEEE ISCAS 2020

5. Japa A, Majumder MK, Sahoo SK, Vaddi R. “Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator” IET Circuits, Devices & Systems. 2020 Aug ;14(5):640-7

2019

6. Subhendu Kumar Sahoo, Pramod Kumar Meher, Ganjikunta, Ganesh Kumar “Lookup Table-Based Efficient Implementation of Multi-Channel Filters for Wireless Networks” IEEE Consumer Electronics Magazine, 2019 Apr 11;8(3):44-9.

7. Aditya Japa, Manoj Kumar Majumder, Subhendu K. Sahoo, Ramesh Vaddi “Tunnel FET Ambipolarity based Energy Efficient and Robust True Random Number Generator against Reverse Engineering Attacks” IET Circuits, Devices & Systems 13, no. 5 (2019): 689-695.

8. Ganesh kumar Ganjikunta; Subhendu Kumar Sahoo; Pramod Kumar Meher “50 Years of FFT Algorithms and Applications”  Circuits, Systems, and Signal Processing. 2019:1-34.

 2018

1.  Sahoo, Subhendu Kumar, Krishna Chaitanya Sankisa, Rasmita Sahoo “A CNTFET Based Quaternary Full Adder” 4th IEEE  International Conference on Circuits, Devices and Systems - ICDCS-18

2. Sahoo, S.K., Dhoot, K. and Sahoo, R., 2018, July. High Performance Ternary Multiplier Using CNTFET. In 2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (pp. 269-274). IEEE.

3. Kaushik, M.K., Yoganandam, Y. and Sahoo, S.K., 2018. Sensing and sharing schemes for spectral efficiency of cognitive radios. International Journal of Electrical and Computer Engineering, 8(5), p.2934.

4.  Kaushik, M.K., Yoganandam, Y. and Sahoo, S.K., 2018. Quality and Availability of spectrum based routing for Cognitive radio enabled IoT networks.

2017

1. Sahoo, Subhendu Kumar, Gangishetty Akhilesh, Rasmita Sahoo, and Manasi Muglikar. "High-Performance Ternary Adder Using CNTFET." IEEE Transactions on Nanotechnology 16, no. 3 (2017): 368-374. (IF- 1.702)

2. Srinivasa Reddy, Kotha, and Subhendu Kumar Sahoo. "An approach for fixed coefficient RNS-based FIR filter." International Journal of Electronics 104, no. 8 (2017): 1358-1376. (IF – 0.414)

3. Ganjikunta, Ganesh Kumar, and Subhendu Kumar Sahoo. "An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications." Integration, the VLSI Journal 57 (2017): 125-131.

4. Subhendu Kumar Sahoo, Gangishetty Akhilesh, Rasmita Sahoo, “Design of An High Performance Carry Generation Circuit for Ternary Full Adder Using CNTFET”, IEEE International Symposium on Nanoelectronic and Information Systems, Dec 2017, Bhopal, India.

5. Subhendu Kumar Sahoo, P. K. Meher, “Lookup Table-Based Low-Power Implementation of Multi-Channel Filters for Software Defined Radio”, IEEE International Symposium on Nanoelectronic and Information Systems, Dec 2017, Bhopal, India.

6. Vishal Shah, Somarouthu Sruthi, Subhendu Kumar Sahoo, “An Efficient Serial-Serial multiplier using Parallel Asynchronous Counter”, 4th International Conference on ‘Microelectronics, Circuits and Systems’, Micro2017, Darjiling, India. 

 2016

1. Kumari, Apurva, and Subhendu Kumar Sahoo. "Real time image and video deweathering: The future prospects and possibilities." Optik-International Journal for Light and Electron Optics 127.2 (2016): 829-839 (IF – 0.742)

2. Manasi Muglikar, Rasmita sahoo, Subhedu Kumar Sahoo, “High Performance Ternary Adder Using CNTFET “ 3rd International Conference on Devices, Circuits and Systems – ICDCS 2016

2015

1. Reddy, Kotha Srinivasa, and Subhendu Kumar Sahoo. "An approach for FIR filter coefficient optimization using differential evolution algorithm." AEU-International Journal of Electronics and Communications 69.1 (2015): 101-108. (IF – 0.757)

2. Kumari, Apurva, and Subhendu Kumar Sahoo. "Fast single image and video deweathering using look-up-table approach." AEU-International Journal of Electronics and Communications 69.12 (2015): 1773-1782. (IF – 0.757)

3. Kumari, Apurva, and S. K. Sahoo. "Real Time Visibility Enhancement for Single Image Haze Removal." Procedia Computer Science 54(Elsevir)  (2015): 501-507.

4. K. S. Reddy, S. K. Sahoo, Selection of cross over ratio factor in differential evolution algorithm for fir filter design, International Journal of Applied Engineering Research 10 (10) (2015) 24861–24870.

5. Ganesh Kumar G and Subhendu Kumar Sahoo“Power-Delay Product Minimization in High-Performance Fixed-Width Multiplier” accepted at International Conference on IEEE Region 10 (IEEE-TENCON 2015) to be held from 1-4 November 2015 in Holiday Inn, Sands CotaiCentralCotai Strip, Macau.

6. Kumar, G. Ganesh, and Subhendu K. Sahoo. "Implementation of a high speed multiplier for high-performance and low power applications." VLSI Design and Test (VDAT), 2015 19th International Symposium on. IEEE, 2015.

7. Kumari, Apurva, and S. K. Sahoo. "Real Time Visibility Enhancement for Single Image Haze Removal." Procedia Computer Science 54 (2015): 501-507.

8. Sahoo, Rasmita, S. K. Sahoo, and Krishna Chaitanya Sankisa. "Design of an efficient CNTFET using optimum number of CNT in channel region for logic gate implementation." VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), 2015 International Conference on. IEEE, 2015.

9. Kumari, Apurva, SidharthSahdev, and S. K. Sahoo. "Improved single image and video dehazing using morphological operation." VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), 2015 International Conference on. IEEE, 2015.

2014

1. Koushik Kumar, ChittineniSahithi, RasmitaSahoo and Subhendu Kumar Sahoo, “Ultra Low Power Full Adder Circuit Using Carbon Nanotube Field Effect Transistor” IEEE International Conference on Power, Control and Embedded Systems To be held at NIT Allahabad on 26th to 28th December 2014

2. ApurvaKumari, Philip Joseph Thomasand S K Sahoo, “Single Image Fog Removal Using Gamma transformation and median filtering” IEEE INDICON 2014, 11th to 13th December 2014.

3. KothaSrinivasa Reddy, Sumit Bajaj, Subhendu Kumar Sahoo, “Shift Add Approach Based Implementation of RNS-FIR Filter using Modified Product Encoder”  IEEE TENCON-2014, Bangkok, Thailand

4. KothaSrinivasa Reddy, Rahul Patel, Tushar Gupta, SubhendukumarSahoo, “A Modified Approach for Reconfigurable FIR Filter Architecture” ”  IEEE TENCON-2014, Bangkok, Thailand

5. Kotha, S.R.; Singhvi, A; Sahoo, S.K., "A New Approach for High Performance RNS-FIR Filter Using the Moduli Set {2 ^k-1, 2^k,2^{k-1}-1}" 2014 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE 2014), vol., no., pp.151,155, 7-8 Apr. 2014.

6. Kotha, S.R.; Vij, S.; Sahoo, S.K., "A study on strategies and Mutant factor in differential evolution algorithm for FIR filter design," Signal Processing and Integrated Networks (SPIN), 2014 International Conference on , vol., no., pp.50,55, 20-21 Feb. 2014

7. Reddy, KothaSrinivasa, Sumit Bajaj, and SahooSubhendu Kumar. "Shift add approach based implementation of RNS-FIR filter using modified product encoder." In TENCON 2014-2014 IEEE Region 10 Conference, pp. 1-6. IEEE, 2014.

8. Reddy, KothaSrinivasa, Rahul Patel, Tushar Gupta, and SahooSubhendu Kumar. "A modified approach for reconfigurable FIR filter architecture." In TENCON 2014-2014 IEEE Region 10 Conference, pp. 1-5. IEEE, 2014.

9. Srinivas Reddy Kotha, DevendraBilaye, Utkarsh Jain and Subhendu Kumar Sahoo  "An Approach for Efficient FIR Filter Design for Hearing Aid Application" 18th International Symposium on VLSI Design and Test (VDAT 2014), IEEE, Coimbatore,India. 

10. Srinivas Reddy Kotha, Sumit Bajaj and Subhendu Kumar Sahoo "An LUT Based RNS FIR Filter Implementation for Reconfigurable Applications"18th International Symposium on VLSI Design and Test (VDAT 2014),IEEE, Coimbatore,India. 

2013

1. Kotha, S.R.; Singhvi, A; Sahoo, S.K., "An efficient RNS-FIR filter implementation using the moduli set {2k − 1, 2k, 2k−1 − 1}," Microelectronics and Electronics (PrimeAsia), 2013 IEEE Asia Pacific Conference on Postgraduate Research in , vol., no., pp.191,195, 19-21,Dec.2013

2. Agarwal, Dhruv, K. S. Reddy, and S. K. Sahoo. "FIR filter design approach for reduced hardware with order optimization and coefficient quantization." Intelligent Systems and Signal Processing (ISSP), 2013 International Conference on. IEEE, 2013.

2012

1. S. K. sahoo, K.S. Reddy, “A High Speed FIR filter Architecture based on Novel Higher Radix Algorithm” IEEE Proceeding of 25th International conference on VLSI design, 7-11 January 2012, Hyderabad, India.

2011

1. Subhendu Kumar Sahoo, Chandra Shekhar, “A Fast Final Adder for A 54-bit Parallel Multiplier for DSP Application,” International Journal of Electronics (Taylor & Francis), Vol. 98, No. 12, December 2011, pp: 1625–38.

2. K.S. Reddy, M.S. Bharath, Subhendu Kumar Sahoo, Shantanu Sinha, Jaipol Reddy, “Design of Low Power, High Performance FIR Filter using Modified Differential Evolution Algorithm” IEEE Proceeding of International Symposium on Electronic System Design (ISED) , 19-21 December 2011, Cochi, India

3. S. K. Sahoo, Chandra Shekhar, “Delay Optimized Array multiplier for Signal and Image processing” IEEE Proceeding of Proceeding of International Conference on Image Information Processing(ICIIP), 3-5 November 2011, Jaypee University of Information Technology, Shimla, Himachal Pradesh, INDIA,

4. SrinivasaReddy.K, S. K. Sahoo, Soumya Chakraborty, “A High Speed, High Radix 32-Bit Redundant Parallel Multiplier” IEEE Proceeding of International Conference on Emerging Trends in Electrical and Computer Technology, 23 Mar - 24 Mar 2011, Nagercoil, India.

2010

1. S. K. Sahoo, Anu Gupta, Abhijit R. Asati and Chandra Shekhar “A Novel Redundant Binary Number to Natural Binary Number Converter” Journal of Signal Processing Systems (Springer), Vol. 59, 2010, pp: 297-307.

2. AbhijitAsati, Subhendu Kumar Sahoo and Chandrashekbar, "An Improved 16-bit Booth Encoded Wallace Tree Multiplier," International Journal of Computational Intelligence and Telecommunication Systems, Vol.1, No. 1, pp. 23-29, January-June 2010. (ISSN: 2229-3078).

3. S.K. Sahoo, R.S.N. Kumar Kattamuri, “ Computation Sharing Multiplier Using Redundant Binary Arithmetic” Proceeding of Asia Pacific Conference on Circuits and Systems (APCCAS 2010), Kuala Lumpur, Malaysia, 6 – 9 November 2010.

2009

1. Subhendu Kumar Sahoo, Chandra Shekhar, SudeeptiKodali, Abhijit R. Asatiand  Anu Gupta, “Dual Channel Addition Based FFT Processor Architecture for Signal and Image Processing” Int. J. High Performance Systems Architecture, Vol. 2, No. 1, 2009, pp:35-45.

2. S.K.Sahoo, P.C.RaghuVamsi Krishna, SairamNeelam, “VLSI implementation of a Novel Personnel Private Branch Exchange Core for Next Generation Telecommunication” Proceeding of Sixth International Conference on Precision, Meso, Micro and Nano Engineering, December, 2009

3. AbhijitAsati,Subhendu Kumar Sahoo,ChandraShekhar, “Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fan-out Load”, IEEE Proceeding of  Second International Conference on Emerging Trends in Engineering & Technology, December 2009, pp. 121-124, Maharashtra, India

4. AshutoshMehra, Anu Gupta, SharvilPatil, Abhishek Mehra,S. K. Sahoo, “A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers”, IEEE Proceeding of  International Conference on Advances in Recent Technologies in Communication and Computing, October 2009, Kottayam, Kerala, India.  

2008

1. Subhendu Kumar Sahoo, Chandra Shekhar, “Design And Analysis Of A Compact Fast Parallel Multiplier For High speed DSP Applications Using Novel Partial Product Generator And 4:2 Compressor,” International Journal of Electronics (Taylor & Francis), Vol. 95, No. 2, February 2008, pp: 139–15.

2. Subhendu Kumar Sahoo, Mayank Kumar Singh, Srikrishna, “High Speed FIR Filter Design Based on Sharing Multiplication using Dual Channel Adder and Compressor” IEEE Proceeding of 9th International Conference on Signal Processing-ICSP2008, pp. 13-16, Beijing, Chaina.

3. Subhendu Kumar Sahoo, AbhijitAshati, RasmitaSahoo, Chandra Shekhar, "A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic," IEEE Proceeding of First International Conference on Emerging Trends in Engineering and Technology-ICETE-2008, pp. 474-479, Nagpur, India

2007 and before:

1. Subhendu Kumar Sahoo, Chandra Shekhar, “Design And Analysis Of A Compact Fast Parallel Multiplier For High speed DSP Applications Using Novel Partial Product Generator And 4:2 Compressor,” 13th International Conference on Advanced Computing and Communication, Coimbatore, India 2005. 

2. Subhendu Kumar Sahoo, Chandra Shekhar , “Novel High-Speed Serial Parallel Multiplier For Moderate Speed Digital Signal Processing,” Asia and South Pacific International Conference on Embedded SoCs (ASPICES), pp. 26, July 5-8, 2005, IISC, Bangalore, India

3. Prasanthi. R ,Anuradha. V, S.K.Sahoo, Chandra Shekhar, “Multiplier Less FFT Processor Architecture For Signal And Image Processing, ” IEEE Proceeding of Second International Conference on Intelligent Sensing and Information Processing- ICISP 05, pp. 326 –330, 2005, Chennai, India. 

4. Subhendu Kumar Sahoo, Anu Gupta, Chandra Shekhar, “A Compact Fast Parallel Multiplier Using Modified Equivalent Binary Conversion Algorithm,” in Proc. Of 8th VLSI Design and Test Workshop, pp 53-64, 2004, Mysore, India.

5. Subhendu Kumar Sahoo, Chandra Shekhar, “Application Specific Parallel Multiplier Design: An Exploration,” IETE Golden Jubilee Seminar on Electronics Design Automation : Issues & Challenges, April 26, 2003, Jaipur, India,

6. Subhendu Kumar Sahoo, A. Routray, R. K. Jena, “Wireless Networking: Implementation on a Laboratory Scale,” PHOTONICS-98: International Conference on Fiber Optics and Photonics, pp. 407-410, December 14-18, 1998, IIT Delhi.

 Prof. M B Srinivas

1. A. Mahesh Kumar and M.B. Srinivas : 'A 12 bit, 1.1 GS/s Low Power Flash ADC', IEEE Transactions on VLSI Design, 2022 (To Appear) 

2. S. Saravanan, Venkat Kalyan Tavva and M.B. Srinivas : 'Techniques to Improve Write and Retention Reliability of STT-MRAM Memory Subsystem', IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 2022 (To Appear)

3. P. Sai Phaneendra, V. Chetan and M.B. Srinivas ; 'Optimization of Reversible Circuits using Gate-Pair Classification', Springer Nature Computer Science, Vol. 3, No. 1, p40, 2022 

4.  'Circular Functional Analysis of OCT Data for Precise Identification of Structural Phenotypes in the Eye', Nature Scientific Reports, 2022

Prof. S. Gurunarayanan

1.   Kanika Monga, Kunal Harbhajanka, Arush Srivastava, Nitin Chaturvedi, S. Gurunarayanan, Design of an MTJ/CMOS based Asynchronous System for Ultra-Low Power Energy Autonomous Applications, Journal of Circuits, Systems and Computers, June, 2020. doi: 10.1142/S0218126621500584 

2.  G.S.S. Chalapathi, Vinay Chamola, Chen-Khong Tham, S. Gurunarayanan and Nirwan Ansari “An                         Optimal Delay   Aware  Task Assignment Scheme for Wireless SDN Networked Edge Cloudlets”    Future                 Generation Computing  Systems.  vol.   102, pp. 862-875, Jan 2020

3. G.S.S Chalapathi, Vinay Chamola, S Gurunarayanan and Biplab Sikdar, “E-SATS: An Efficient and Simple Time Synchronization Protocol for Cluster-based Wireless Sensor Networks,” IEEE Sensors Journal, vol. 19, no. 21, pp. 10144-10156, 1 Nov.1, 2019.

4. G.S.S Chalapathi, Vinay Chamola and S Gurunarayanan, “A Testbed validated simple time synchronization protocol for clustered wireless sensor networks for IoT,” Journal of Intelligent and Fuzzy Systems, IOS Press, vol. 36, no. 5, pp. 4531-4543, 2019

5. G.S.S Chalapathi, Bernhard Etzlinger, S Gurunarayanan and Andreas Springer, “Integrated Cooperative Synchronization for Wireless Sensor Networks,” IEEE Wireless Communication Letters, vol. 8, no. 3, pp. 701-704, June 2019.

6. D.C. Kiran, S. Gurunarayanan, Janardan Prasad Misra, and Abhijeet Nawal ," Global Scheduling Heuristics for Multicore Architecture", Hindawi Publishing Corporation, Scientific Programming, Volume 2015, Article ID 860891 , http://dx.doi.org/10.1155/2015/860891

7. D.C. Kiran, S. Gurunarayanan, J.P.Misra & Munish Bhathia "Register Allocation for Fine Grained Threads on Multicore Processors". Journal of King Saud University - Computer and Information Sciences, Elsevier,Volume 27, Issue 3 2015. https://core.ac.uk/download/pdf/82071516.pdf

8. Nitin Chaturvedi, Arun Subramanian, S Gururnarayanan, “Selective cache line replication scheme in Shared Last Level Cache”, in Procedia of Computer Science, Elsevier, Volume 46, pp.1095-1107, 2015. (Scopus)

9. Nitin Chaturvedi, Arun Subramanian, S Gururnarayanan, “   An  Efficient  data  access  policy  for shared last Level      Cache”,   in WSEAS transaction on computers, Volume 14, 2015.

10. Nitin Chaturvedi, S Gurunaryanan, “An Efficient adaptive block pinning for multi-core architectures”,  in Journal of     Microprocessor and Microsystems, Elsevier, Volume 39, Issue 3, 2015. (SCI)

11. Nitin Chaturvedi, S Gurunaryanan “An Adaptive Migration-Replication Scheme (AMR) for      Shared Cache in Chip     Multiprocessors” in Journal of Parallel Computing, Springer, Volume 71, Issue   10 pp. 3904-3933,  Oct. 2015. (SCI)

12. Nitin Chaturvedi, S Gurunaryanan “An A Locality-Aware Variable Granularity Cache Architecture” Electronics Letter-    IET, January 2015

13. Nitin Chaturvedi, S Gururnarayanan, “ Adaptive Block Pinning :  A  Novel  Shared  Cache  Partitioning  Techniques for  CMP” in European Journal of Scientific Research, Volume 117, Issue 1, June 2014.

14. Nitin Chaturvedi, S Gururnarayanan, “ Study of  Various Factors Affecting Performance of Multi-Core Architectures”   in International Journal of Distributed and Parallel Systems, Volume 4, No 4, July 2013.

15. Jai Gopal Pandey, Abhijit Karmakar, Chandra Shekhar and S. Gurunarayanan “Platform - Based   Design Approach    for Embedded Vision Applications”Journal of Image and Graphics Volume 1, No.1,   March 2013. 

16.     Nitin Chaturvedi, Jithin Thomas, S Gururnarayanan, “ Adaptive Block Pinning Based :  Dynamic Cache Partitioning     for Multi - Core  Architectures”   in  International  Journal of  Computer Science  &  Information  Technology       (IJCSIT),     Volume  2,    No 6, December 2010.

17.   Nitin Chaturvedi, Jithin Thomas, S Gururnarayanan, “Adaptive Zone-Aware Multi-bank on Chip last level L2 cache     Partitioning for Chip Multiprocessors” in International Journal of Computer Applications ,Volume 6, No-9,           September 2010.

18.  Biju Raveendran, T S B Sudarshan, and S Gurunarayanan. “Cache Memory Design with Late Replacements for       Embedded Systems” International Journal of Lateral Computing, Vol.2, No. 2, August 2006.

19.   A K Singh, S Gurunarayanan, V Ramachandran and M Umashankar. “Edge Potential Effects on the operation  of short   channel devices” Microelectronics International Vol.20, Number 3, 2003.

Conferences

1.   Pranshu, Shaishta, Nitin, S Gurunarayanan, “An Exploration of Neuromorphic Systems and Related Design Issues/Challenges in Dark Silicon Era” in 3rd International Conference on Communication Systems, ICCS-2017, 14-16 October 2017, Pilani, India. 

2.    Suvi Jain, Nitin Chaturvedi, S Gurunarayanan, “Design and Analysis of 6T SRAM Cell with NBL Write Assist Technique Using FinFET” in International Conference on Computer, Communications and Electronics, COMPTELIX 2017, 1-2 July 2017,Jaipur,India .(IEEE-Xplore)

3.   Divya Suneja, Nitin Chaturvedi, S Gurunarayanan, “A Comparative Analysis of Read/Write Assist   Techniques on Performance & Margin in 6T SRAM Cell Design” in International Conference on   Computer, Communications and Electronics, COMPTELIX 2017, 1-2, July 2017,  Jaipur,             India (IEEE -Xplore) 

4.  Nikunj, Nitin Chaturvedi, S Gurunarayanan, “Design Of Non-Volatile Asynchronous Circuit Using CMOS-FDSOI/FinFET Technologies” in IEEE International Conference on Computing, Analytics and Security Trends, CAST-2016, 19-21 December 2016, Pune, India (IEEE-Xplore)

5.   Pranshu, Shaishta, Nitin Chaturvedi, S Gurunarayanan, “An Investigation of Power- Performance Aware     Accelerator/Core Allocation Challenges in Dark Silicon Heterogeneous Systems” in 2nd IEEE International       symposium on nanoelectronic and information systems, IEEE-INIS-2016, 19-21 December 2016, IIITM    Gwalior,India (IEEE-Xplore) 

 6.   GSS Chalapathi,  R. Manekar,  V. Chamola,  K.R. Anupama  and  S Gurunarayanan, "Hardware Validated   Efficient  Simple Time Synchronization Protocol for clustered WSN," IEEE TENCON, 2016, Singapore, Nov. 22- 25, 2016.

 7.   R. Manekar, GSS Chalapathi, V. Chamola, K.R. Anupama and S Gurunarayanan,“A Simple Time Synchronization Algorithm for WSNs in Smart Grid Applications,” EEE Symposium on Emerging  Topics in Smart and Sustainable  Grids, Singapore, Sept. 2016  

    8.    J. G. Pandey,  A. Karmakar,  C. Shekhar,  and S. Gurunarayanan,  An Embedded   Frame work for Accurate Object Localization using Center of Gravity Measure with Mean Shift Procedure, IEEE 19th International Symposium on   VLSI  Design and Test, Ahmedabad,   India, 26-29 June 2015,   pp. 1-6.      

       9.   J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan,    “Architectures  for      Embedded   Vision Application using FPGA-based Platform” IEEE 28th Int’l Conf. on VLSI Design and  14th Int’l Conf. on Embedded Systems (VLSI Design 2015), Bangalore, India, 3-7 Jan. 2015. 

 10.   J.G. Pandey, A Karmakar, C Shekhar, S Gurunarayanan, “An FPGA-based architecture for local  similarity measure for image/video processing applications” 2015, 28th International Conference  on  VLSI Design, 339-344, Bangalore, India. 

 11.     J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, Architectures and algorithms for    image and video processing using FPGA-based platform IEEE 18th International Symposium on  VLSI Design and Test, Coimbatore, India,16-18 July 2014  pp.1-1  

   12.   J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “A novel architecture for FPGA   implementation of Otsu’s global automatic image thresholding algorithm,” in Proceedings of IEEE 27th International Conf. on VLSI Design and 13th International Conf. on Embedded Systems        (VLSI Design 2014), Mumbai, India, 5-9 Jan. 2014, pp. 300-305. (IEEE Xplore) [Impact  factor: 0.40]   (For  Year 2012)

 13.    J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “An FPGA-based architecture for   kernel-smoothed local histogram computation,”Accepted for publication in IEEE International    Symposium on Circuits and Systems (ISCAS-2014), Melbourne, Australia, 01-05 June, 2014.         (IEEE   -  Xplore) [Impact factor: 0.27] (For Year 2012). 

 14.     J. G. Pandey, A. Karmakar, A. K. Mishra, C. Shekhar, and S. Gurunarayanan, “Implemention    of an  improved connected component labeling algorithm using FPGA based platform,” Accepted for  Publication in IEEE International Conf. on Signal Processing and  Communications (SPCOM, 2014), IISc-Bangalore, India, 22-25 July 2014. (IEEE- Xplore)

 15.   J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “An FPGA-based novel           architecture for the fixed-point binary antilogarithmic computation,” in Proceedings of IEEE  International Conf. on Electronic Systems, Signal Processing and Computing Technologies        (ICESC),  Nagpur, India,     09-11 Jan. 2014, pp. 23-28. (IEEE- Xplore) [Best Paper Award]

 16.    J. G. Pandey, A. Karmakar, C. Shekhar, and S. Gurunarayanan, “An FPGA-based fixed-point  architecture for binary logarithmic computation,” in Proceedings of 2nd IEEE International   Conf.  in Image Information Processing (ICIIP-2013),  Shimla, India, 09-12 Dec. 2013, pp.    383- 388. (IEEE -Xplore)

 17.    Nitin Chaturvedi, S Gurunarayanan, “An Adaptive Block Pinning Cache for Reducing Network   Traffic in Multi-Core Architectures” 2013 IEEE International Conference on Computational Intelligence and Communication Network, ICCN- 2013, September 27-29, 2013, Mathura, India (IEEE –Xplore)

 18.   Nitin Chaturvedi, S Gurunarayanan, “An Adaptive Cache Coherence Protocol with adaptive Cache for Multi-core Architectures” in proceedings of International Conference on Advanced Electronic Systems, ICAES-2013 September 21-23, 2013, CEERI, Pilani,India (IEEE –Xplore) 

 19.    Munish Bhathia, D.C.Kiran, S Gurunarayanan, and J.P.Misra, "Fine Grain Thread Scheduling on     Multicore Processors: Cores With Multiple Functional Units". Compute '13: Proceedings of the  6th  ACM India Computing Convention, Vellore, Tamilnadu, India. August 2013 Article No.:        20  Pages  1–6 . https://doi.org/10.1145/2522548.2523137. http://dl.acm.org/citation.cfm?              doid=2522548.2523137

 20.  D.C. Kiran, S. Gurunarayanan, J.P.Misra, and D.Yashas "Integrated Scheduling and Register        Allocation For Multicore Architecture". In IEEE Conference on Parallel Computing Technologies  PARCOMPTECH-2013, Organized by C-DAC in IISC Bangalore, February  2013.  https://ieeexplore.ieee.org/document/6621400

 21.  D.C. Kiran, S. Gurunarayanan, and J.P.Misra, Compiler Driven Inter Block Parallelism for Multicore Processors. In 6th International Conference on Information Processing, published in the Communications in Computer and Information Science (CCIS), Springer-Verlag, Bangalore, India, August 2012. http://link.springer.com/chapter/10.1007/978-3-642-31686-9_50  

22.  D.C. Kiran, S. Gurunarayanan, Faizan Khaliq, and Abhijeet Nawal, Compiler Efficient and Power Aware Instruction Level Parallelism for Multicore Architectures. In The International Conference of Eco-friendly Computing and Communication Systems, (ICECCS) 2012, Kochi, India, August 9-11, 2012. Proceedings published in the Communications in Computer and Information Science (CCIS), Springer-Verlag, pp.9-17 http://link.springer.com/chapter/10.1007%2F978-3-642-32112-2_2

 23. D.C. Kiran, S. Gurunarayanan, J.P.Misra and Faizan Khaliq, An Efficient Method to Compute Static Single Assignment Form for Multicore Architecture. In 1st IEEE International Conference on Recent Advances in Information Technology, Dhanbad, India. March, 2012. pp. 776-789, http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6194553

24. Nitin Chaturvedi, Prashant Gupta, S Gurunarayanan, “Efficient Cache Migration Policy for Chip Multi-Processors” 2011 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC-11, 15-18 December 2011. Kanyakumari, Tamilnadu, India.

25. D.C. Kiran, S. Gurunarayanan, and J.P.Misra, Taming Compiler to Work with Multicore Processors. IEEE Conference on Process Automation, Control and Computing.  Coimbatore,  Tamilnadu, India  20-22  July  2011. http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5978868 

26. D.C.Kiran, B. Radheshyam. Gurunarayanan, and J.P.Misra, Compiler Assisted Dynamic   Scheduling for Multicore Processors. IEEE Conference on Process Automation, Control and  Computing, Coimbatore,  Tamilnadu, India, July,20- 22,   2011.   http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5978903

27.  Nitin Chaturvedi, Pradeep Harinderan, S Gururnarayanan, “A Novel shared L2 NUCA cache       partitioning scheme for Multi-core Architectures” in proceedings of International Conference on   Emerging Trends in Engineering (ICETE),Maharashtra, India, Feb.20-21, 2010. pp. 183-188.

28.   Biju Raveendran , Sundar Balasubramaniam , and S. Gurunarayanan. “Evaluation of Priority   Based Real Time Scheduling Algorithms: Choices and Tradeoffs.” In Proceedings of the 23rd  Annual ACM Symposium on Applied Computing (ACM SAC'08), Brazil, Mar-2008, vol. 1, pp.    302 - 307. 

 29.    Biju Raveendran, T S B Sudarshan, Avinash Patil, Komal Randive, and S Gurunarayanan. “Predictive    Placement Scheme for Set-Associative Cache for Energy  Efficient   Embedded System.” Proceedings of International Conference on Signal Processing, Communications  and Networking, (ICSCN 2008),January 4-6, 2008, Chennai, Tamilnadu, India pp. 152-157,   Available online in IEEEXPLORE.

30. Biju Raveendran, T S B Sudarshan, Dlip Kumar, Priyanaka Tugudu and S Gurunarayanan. “LLRU: Late LRU Replacement Strategy for Power Efficient Embedded Cache.”Proceedings of 15th IEEE              International Conference On Advanced Computing (ADCOM), IIT-Kharagpur,India Dec-2007,  pp. 339-344, Available online in IEEEXPLORE.

 31. Biju Raveendran, T S B Sudarshan, Avinash Patil, Komal Randive, and S Gurunarayanan. “An     Energy Efficient Selective Placement Scheme for Set-Associative Data Cache in Embedded   System.” Proceedings of ESA'07- The 2007 International Conference on Embedded Systems   and  Applications, USA, (Published by CSREA Press, Jun-2007, pp. 188–194.

32. Biju Raveendran, J P Misra, Karan Bhatnagar and S Gurunarayanan. “EFFS: Efficient Flash File   System for Wireless Sensor Nodes.” Proceedings of ESA'07- The 2007 International Conference  on Embedded Systems and Applications, USA, (Published by CSREA Press, Jun-2007, pp. 159– 165. 

 33. Biju Raveendran, T S B Sudarshan, and S Gurunarayanan. “Selective Placement Data Cache for   Low  Energy Embedded System”. Proceedings of 14th IEEE International Conference On      Advanced   Computing (ADCOM), NITK, Surathkal, India. Dec-20-23, 2006, pp. 473-476,  Available online  in IEE-EXPLORE. 

34. Ninad B Kothari, T S B Sudarshan, S Gurunarayanan, and S Chandrashekhar. “SoC Design of a   Low  Power Wireless Sensor Network Node for Zigbee Systems.” Proceedings of 14th IEEE   International Conference On Advanced Computing (ADCOM),  NITK, Surathkal, India.  Dec- 20-23-2006, pp.  462-466. Available online in IEE-EXPLORE.

 35. Biju Raveendran , Sundar Balasubramaniam , K Durga Prasad and S. Gurunarayanan. “Variants of  Priority Scheduling Algorithms for Reduced Context Switches in Real Time System.” 8th   International Conference on Distributed Computing and Networking (ICDCN), Lecture  Notes in Computer Science, Springer-Verlag. IIT - Guwahati, India. Dec-2006, pp. 466-478.

 36. Biju Raveendran , Sundar Balasubramaniam , K Durga Prasad and S. Gurunarayanan. “A Context-  Switch Reduction Heuristic for Power-Aware Off-line Scheduling.” 11th Asia-Pacific Computer  Systems Architecture Conference (ACSAC), Lecture Notes in Computer Science, Vol. 4186,    Springer-Verlag. Shanghai, China, Sep-2006, pp. 404-411.

37. Ninad B Kothari, T S B Sudarshan, Shipra Bhal, Tejesh E C, and S Gurunarayanan. “Design of an  Efficient Low-Power AES Engine for Zigbee Systems.” Proceedings of 10th IEEE VLSI Design &   Test Symposium (VDAT), Goa, India. Aug-2006, pp. 264-272. 

38. Biju Raveendran, T S B Sudarshan, and S Gurunarayanan. “Cache Memory Design with Late  Replacements for Embedded Systems.” Proceedings of 2nd International Conference on        Embedded  Systems, Mobile Communication and Computing (ICEMC2), Bangalore, India.  Aug-  2006, pp. 76- 90.

39. Gurunarayanan , R Mehrotra and S Chandrashekhar. “Modelling of ESD Protection Circuits.”Proceedings of 8th International Workshop on Physics of Semiconductor    Devices,  New Delhi, India. 1995.

40. Gurunarayanan , R Mehrotra and S Chandrashekhar.”Drain Induced Barrier lowering in short channel NMOS Devices.”Proceedings of 7th International Workshop on Physics of Semiconductor  Devices. New Delhi, India Dec. 14-18, 1993. 75-76.  Narosa Publishing House, 1994

 Prof.Surya Shankar Dan

Publication details (Reverse chronological order)

21. Arun Mohan*, Saroj Mondal, Surya Shankar Dan, and Roy P. Paily, "Design Considerations for Efficient Realization of Rectifiers in Micro-Scale Wireless Power Transfer Systems - A Review", IEEE Sensors Journal, Nov 2022 (https://doi.org/10.1109/JSEN.2022.3222938) 

20.Soumi Saha, Vivek Adepu, Khush Gohel, Parikshit Sahatiya*, and Surya Shankar Dan*, "Demonstration of a 2D SnS/MXene Nanohybrid Asymmetric Memristor", IEEE Transactions on Electron Devices, vol. 69, no. 10, pp. 5921-5927, Oct 2022 (https://doi.org/10.1109/TED.2022.3199710) 

19.Simhadri Hariprasad and Surya Shankar Dan*, "Superior Analog Performance due to Source-Gate Overlap in Vertical Line-Tunneling FETs and Their Circuits", Springer Silicon, Jul 2022 (https://doi.org/10.1007/s12633-022-01954-7) 

18.Ramakant Yadav, Surya Shankar Dan*, and Simhadri Hariprasad, "Low and High VT GOTFET Devices Outperform Standard CMOS Technology in Ternary Logic Applications", IETE Technical Review, Aug 2021 (https://doi.org/10.1080/02564602.2021.1960903) 

17.Simhadri Hariprasad, Surya Shankar Dan*, Ramakant Yadav, and Ashutosh Mishra, "Double-Gate Line-Tunneling FET (DGLTFET) Devices for Superior Analog Performance", Wiley International Journal on Circuits Theory and Applications, vol. 49, issue 7, pp. 2094-2111, Apr 2021 (https://doi.org/10.1002/cta.3002) 

16.Sanjay Vidhyadharan and Surya Shankar Dan*, "An Efficient Ultra-Low Power and Superior Performance Design of Ternary Half Adder Using CNFET and Gate-Overlap TFET Devices", IEEE Transactions on Nanotechnology, vol. 20, pp. 365-376, Jan 2021 (https://doi.org/10.1109/TNANO.2020.3049087) 

15.Sanjay Vidhyadharan, Surya Shankar Dan*, Ramakant Yadav, and Simhadri Hariprasad, "An Innovative Ultra-Low Voltage GOTFET based Regenerative-Latch Schmitt Trigger", Elsevier Microelectronics Journal, vol. 104, pp. 104879, Oct 2020 (https://doi.org/10.1016/j.mejo.2020.104879) 

14.Ramakant Yadav, Surya Shankar Dan*, Sanjay Vidhyadharan, and Simhadri Hariprasad, "Suppression of Ambipolar Behavior and Simultaneous Improvement in RF Performance of Gate-Overlap Tunnel Field Effect Transistor (GOTFET) Devices", Springer Silicon, vol. 13, pp. 1185–1197, Jul 2020 (https://doi.org/10.1007/s12633-020-00506-1) 

13.Sanjay Vidhyadharan, Surya Shankar Dan*, Abhay S. V., Ramakant Yadav, and Simhadri Hariprasad, "Novel gate-overlap tunnel FET based innovative ultra-low-power ternary flash ADC", Elsevier Integration, the VLSI Journal, vol. 73, pp. 101-113, Jul 2020 (https://doi.org/10.1016/j.vlsi.2020.03.006) 

12.Sanjay Vidhyadharan, Surya Shankar Dan*, Ramakant Yadav, and Simhadri Hariprasad, "A novel ultra-low-power gate overlap tunnel FET (GOTFET) dynamic adder", Taylor and Francis International Journal of Electronics, vol. 107, no. 10, pp. 1663-1681, Mar 2020 (https://doi.org/10.1080/00207217.2020.1740800) 

11.Ramakant Yadav, Surya Shankar Dan*, Sanjay Vidhyadharan, and Simhadri Hariprasad, "Innovative multi-threshold gate-overlap tunnel FET (GOTFET) devices for superior ultra-low power digital, ternary and analog circuits at 45-nm technology node", Springer Journal of Computational Electronics, vol. 19, pp. 291-303, Jan 2020 (https://doi.org/10.1007/s10825-019-01440-1)

10.Sanjay Vidhyadharan, Ramakant Yadav, Simhadri Hariprasad, and Surya Shankar Dan*, "An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications", Springer Analog Integrated Circuits and Signal Processing, vol. 102, pp. 111-123, Nov 2019 (https://doi.org/10.1007/s10470-019-01561-4) 

9.Sanjay Vidhyadharan, Ramakant Yadav, Simhadri Hariprasad, and Surya Shankar Dan*, "A nanoscale gate overlap tunnel FET (GOTFET) based improved double tail dynamic comparator for ultra-low-power VLSI applications", Springer Journal of Analog Integrated Circuits and Signal Processing, vol. 101, pp. 109-117, Jun 2019 (https://doi.org/10.1007/s10470-019-01487-x) 

8.Arnab Biswas*, Surya Shankar Dan, Cyril LeRoyer, Wladyslaw Grabinski, and Adrian Mihai Ionescu, "TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model", Elsevier Journal of Microelectronic Engineering, vol. 98, pp. 334-337, Oct. 2012 (https://doi.org/10.1016/j.mee.2012.07.077) 

7.Surya Shankar Dan*, Arnab Biswas, Cyril LeRoyer, Wladyslaw Grabinski, and Adrian Mihai Ionescu, "A Novel Extraction Method and Compact Model for the Steepness Estimation of FDSOI TFET Lateral Junction", IEEE Electron Device Letters, vol. 33, no. 2, pp. 140-142, Feb. 2012 (https://doi.org/10.1109/LED.2011.2174027) 

6.Surya Shankar Dan* and Santanu Mahapatra, "Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor-single electron transistor integrated circuits", IET Circuits Devices Systems, vol. 4, no. 5, pp. 449-457, Sep. 2010 (http://doi.org/10.1049/iet-cds.2009.0341) 

5.Surya Shankar Dan* and Santanu Mahapatra, "Analysis of Energy Quantization Effects on Single-Electron Transistor Circuits", IEEE Transactions on Nanotechnology, vol. 9, no. 1, pp. 38–45, Jan. 2010 (https://doi.org/10.1109/TNANO.2009.2022833) 

4.Surya Shankar Dan* and Santanu Mahapatra, "Modeling and analysis of energy quantization effects on single electron inverter performance", Physica E: Low-dimensional Systems and Nanostructures, vol. 41, no. 8, pp. 1410-1416, Aug. 2009 (https://doi.org/10.1016/j.physe.2009.04.004) 

3.Surya Shankar Dan* and Santanu Mahapatra, "Impact of Energy Quantization on the Performance of Current-Biased SET Circuits", IEEE Transactions on Electron Devices, vol. 56, no. 8, pp. 1562-1566, Aug. 2009 (https://doi.org/10.1109/TED.2009.2023954) 

2.Sitangshu Bhattacharya*, Surya Shankar Dan, and Santanu Mahapatra, "Influence of band non-parabolicity on the quantized gate capacitance in δ-doped MODFED of III–V and related materials", Journal of Applied Physics, vol. 104, no. 7, p. 074304, Jul 2008 (https://doi.org/10.1063/1.2986154) 

1.Chaitanya Sathe, Surya Shankar Dan*, and Santanu Mahapatra, "Assessment of SET Logic Robustness Through Noise Margin Modeling", IEEE Transactions on Electron Devices, vol. 55, no. 3, pp. 909–915, Mar. 2008 (https://doi.org/10.1109/TED.2007.915086) 

Book Chapters

Publication details (Reverse chronological order)

5.Simhadri Hariprasad*, Ramakant Yadav, and Surya Shankar Dan, "Novel Gate-Overlap Tunnel FETs for Superior Performance Analog, Digital and Ternary VLSI Circuit Applications Under Low-Power Consumption", CRC Press (Recently accepted)

4.Sanjay Vidhyadharan and Surya Shankar Dan*, 'Gate-Overlap Tunnel Field- Effect Transistors (GOTFETs) for Ultra-Low-Voltage and Ultra-Low-Power VLSI Applications', Chapter 8, Taylor & Francis, (https://doi.org/10.1201/9781003168225-8)

3.Arun Mohan*, Saroj Mondal and Surya Shankar Dan, 'On-Chip Threshold Compensated Voltage Doubler for RF Energy Harvesting', Springer VLSI Design and Testing, vol. 1066, A. Sengupta, S. Dasgupta, V. Singh, R. Sharma, and S. Kumar Vishvakarma, Eds. Singapore: Springer Singapore, 2019, pp. 180–189, Aug 2019, (https://doi.org/10.1007/978-981-32-9767-8_16) 

2.Sanjay Vidhyadharan*, Ramakant Yadav, Gangishetty Akhilesh, Vaibhav Gupta, Anand Ravi and Surya Shankar Dan, 'Part II: Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology', Springer Physics of Semiconductor Devices, vol. 215, R. K. Sharma and D. S. Rawal, Eds. Cham: Springer International Publishing, 2019, vol. 215, pp. 619–628, Feb 2019, (https://doi.org/10.1007/978-3-319-97604-4_96) 

1.Ramakant Yadav*, Sanjay Vidhyadharan, Gangishetty Akhilesh, Vaibhav Gupta, Anand Ravi and Surya Shankar Dan, 'Part I: Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology', Springer Physics of Semiconductor Devices, vol. 215, R. K. Sharma and D. S. Rawal, Eds. Cham: Springer International Publishing, 2019, vol. 215, pp. 611–618, Feb 2019, (https://doi.org/10.1007/978-3-319-97604-4_95) 

Doctoral Thesis Supervised

Submission details (Reverse chronological order)

4.Simhadri Hariprasad*, "Superior Analog, Digital, and Ternary Circuit Designs Using Advanced Nano-electronic Gate Overlap Tunnel FET Devices for Ultra-Low Power Applications" (Thesis under review)

3.Arun Mohan*, "Energy Processing Circuits for a Multi-Band RF Energy Harvesting Systems" (Thesis under review, co-supervised with Dr. Saroj Mondal)

2.Ramakant Yadav*, "Novel Gate Overlap Tunnel FET Device Designs for Ultra-Low-Power Digital, Ternary, and Analog VLSI Applications" (Defended in Jan 2022) 

1.Sanjay Vidhyadharan*, "Novel Gate-Overlap Tunnel FETs and Their Circuits for Ultra-Low Power VLSI Applications" (Defended in Jun 2020) 

Conference Seminars

Presentation details (Reverse chronological order)

15.Simhadri Hariprasad* and Surya Shankar Dan, 'Superior Analog Performance due to Source-Gate Overlap in Vertical Line-TFETs and Their Circuits', 35th International Conference on VLSI Design (VLSID 2022), Virtual

14.Soumi Saha*, Vivek Adepu, Khush Gohel, Parikshit Sahatiya, and Surya Shankar Dan, 'Demonstration of a 2D SnS/MXene Asymmetric Nanohybrid Memristor', XXIst International Workshop on Physics of Semiconductor Devices (IWPSD 2021), New Delhi

13.Simhadri Hariprasad*, Surya Shankar Dan, Ramakant Yadav and Sanjay Vidhyadharan, 'Innovative Strained SiGe Nanoscale Low & High Vt Gate Overlap TFET Structures at 45 nm Standard CMOS Technology for Ultra-Low Power Yet High Performance Analog, Digital and Ternary VLSI Applications', XXth International Workshop on Physics of Semiconductor Devices (IWPSD 2019), Kolkata

12.Sanjay Vidhyadharan*, Ramakant Yadav, Abhay S. V., A. Krishna Shyam, Mohit P. Hirpara and Surya Shankar Dan, 'An Efficient Design Approach for Implementation of 2 bit Ternary Flash ADC Using Optimized Complementary TFET Devices', 32nd International Conference on VLSI Design (VLSID 2019), New Delhi

11.Ramakant Yadav*, Sanjay Vidhyadharan, A. Krishna Shyam, Mohit P. Hirpara, Tanmay Chaudhary and Surya Shankar Dan, 'Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked With Standard 45 nm CMOS Technology for Ternary Logic Applications', 32nd International Conference on VLSI Design (VLSID 2019), New Delhi

10.Arun Mohan*, Saroj Mondal and Surya Shankar Dan, ‘On-Chip Threshold Compensated Voltage Doubler for RF Energy Harvesting’, 23rd International Symposium on VLSI Design and Test (VDAT 2019), Indore

9.Ramakant Yadav*, Sanjay Vidhyadharan, Gangishetty Akhilesh, Vaibhav Gupta, Anand Ravi and Surya Shankar Dan, ‘Part I: Optimization of the Tunnel FET Device Structure for Achieving Circuit Performance Better Than the Current Standard 45 nm CMOS Technology’, XIXth International Workshop on Physics of Semiconductor Devices (IWPSD 2017), New Delhi

8.Sanjay Vidhyadharan*, Ramakant, Gangishetty Akhilesh, Vaibhav Gupta, Anand Ravi and Surya Shankar Dan, ‘Part II: Benchmarking the Performance of Optimized TFET-Based Circuits with the Standard 45 nm CMOS Technology Using Device & Circuit Co-simulation Methodology’, XIXth International Workshop on Physics of Semiconductor Devices (IWPSD 2017), New Delhi

7.Arnab Biswas*, Surya Shankar Dan, Cyrille Le Royer, Wladyslaw Grabinski and Adrian Ionescu, ‘TCAD Simulation of SOI TFETs and Calibration of non-local Band-to-Band Tunneling Model’, Micro and NanoElectronic Conference, (MNE 2013), Berlin, Germany

6.Jayita Das*, Debasree Burman and Surya Shankar Dan, ‘A Physics-Based Compact Analytical Model for Tunnel Field Effect Transistors Based on band-to-Band Tunneling’, International Conference on VLSI and Signal Processing (ICVSP 2014), Kharagpur

5.Surya Shankar Dan* and Santanu Mahapatra, ‘Impact of energy quantization in SET island on hybrid CMOS-SET integrated circuits’, XVth International Workshop on the Physics of Semiconductor Devices (IWPSD 2009), New Delhi

4.Surya Shankar Dan* and Santanu Mahapatra, ‘Analysis of the energy quantization effects on single electron inverter performance through noise margin modeling’, 22nd International Conference on VLSI Design (VLSID 2009), pp. 493-498, New Delhi

3.Surya Shankar Dan* and Chandan Kumar Sarkar, ‘Transport mechanism for Boolean logic implementation using resonant tunneling diode coupled single-electron quantum dot device’, XIIIth International Workshop on the Physics of Semiconductor Devices (IWPSD 2005), Madras

2.Madhabi Ray*, Surya Shankar Dan and Chandan Kumar Sarkar, ‘Realization of quantum dot Boolean logic gate for image processing applications’, XIIIth International Workshop on the Physics of Semiconductor Devices (IWPSD 2005), Madras

1.Surya Shankar Dan* and Saibal Pradhan, ‘Implementation of a 16-bit SOC microprocessor system using FPGA’, International Conference on Communication, Devices Intelligent Systems (CODIS 2004), Kolkata

Dr. Sumit Kumar Chatterjee

1. Sumit K Chatterjee and Indrajit Chakrabarti, Power efficient motion estimation algorithm and architecture based on pixel truncation, in IEEE Trans. On Consumer Electronics, vol. 57, no. 4, pp. 1782-1790, Nov. 2011.

2. Sumit K Chatterjee, Implementation of weighted constrained one-bit transformation based fast motion estimation in IEEE Trans. On Consumer Electronics, vol. 58, no. 2, pp. 646-653, May 2012.

3. Sumit K Chatterjee and Indrajit Chakrabarti, Algorithm and architecture for quarter pixel motion estimation for H.264/AVC, in Proc National Conference on Computer Vision, Graphics & Image Processing, (NCVGIP '13), held at IIT Jodhpur, India.

4. Sravan K. Vittapu and Sumit K Chatterjee, A new one bit transform for low complexity block based motion estimation for HEVC, in IEEE International Conference on Communication and Electronics (ICCES)-2017.

5. Sravan K. Vittapu and Sumit K. Chatterjee, “Complexity reduction for HEVC encoder using multiplication free one-bit transformation,” in J. Electron. Imaging 27(6), 063028 (2018), doi: 10.1117/1.JEI.27.6.063028.

6. Sumit K. Chatterjee and Sravan K. Vittapu, “An Efficient Motion Estimation Algorithm for Mobile Video Applications" in 2019 Second International Conference on Advanced Computational and Communication Paradigms (ICACCP), pp. 1-5. IEEE, 2019.

7. Sravan K. Vittapu and Sumit K. Chatterjee, “Complexity reduction for HEVC encoder using one-dimensional filtering based constrained one-bit transform”, Microsystem Technologies, Sept (20), doi: https://doi.org/10.1007/s00542-020-05035-w(0123456789().,-volV)(0123456789().,-vol V).

8. Sumit K. Chatterje, Sravan K. Vittapu, and Souvik Kundu, “Prediction-biased diamond search algorithm: a new approach to reduce motion estimation complexity”, Microsystem Technologies, Jan (21), doi: https://doi.org/10.1007/s00542-020-05167-z(0123456789().,-volV)(0123456789().,-vol V).

9. Sravan K. Vittapu, Souvik Kundu & Sumit K. Chatterjee, “A New Low Complexity Bit-truncation Based Motion Estimation and Its Efficient VLSI Architecture”, IETE Journal of Research, Aug 21, doi: 10.1080/03772063.2021.1965040.

10. Sumit K. Chatterje and Sravan K. Vittapu, “FPGA Implementation of EFSME for High Efficient Video Coding Standard”, in Multimedia Tools and Applications (accepted for publication).

Dr. Soumya J

International Journals:

14. Jagadeesh Samala, P. Veda Bhanu, Soumya J., Lingareddi C, Reinforcement Learning based Fault-Tolerant Routing Algorithm for Mesh based NoC and its FPGA Implementation, IEEE Access, 9,44724-44737 (2022), - https://doi.org/10.1109/ACCESS.2022.3168992

 13. Jagadeesh Samala, P. Veda Bhanu, Soumya J., NoC Application Mapping Optimization using Reinforcement Learning, ACM Transactions on Design Automation of Electronic Systems, 2022, Accepted. - https://dl.acm.org/doi/10.1145/3510381

12. P. Veda Bhanu, Rahul Govindan,  Rajat Kumar, Vishal Singh, Soumya J., Lingareddi C, Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA. IEEE Access, 9, 76759-76779, (2021)

- https://ieeexplore.ieee.org/document/9438664

11. P. Veda Bhanu, Rahul Govindan, Plava Kattamuri, Soumya J., Lingareddi C, Flexible Spare Core Placement in Torus Topology based NoCs and its Validation on an FPGA, IEEE Access, 9, 45935-45954, (2021) - https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9380138

10. P. Veda Bhanu, Soumya J., Fault-Tolerant Application Mapping onto Mesh-of-Tree Topology based Network-on-Chip Design, Journal of Systems Architecture, 116, 102026, (2021) - https://www.sciencedirect.com/science/article/pii/S138376212100031X#:~:text=An%20Integer%20Linear%20Programming%20(ILP,%2DTree%20(MoT)%20network.

9.  P. Veda Bhanu, Pranav Venkatesh Kulkarni, Soumya J., Butterfly-Fat-Tree topology based fault-tolerant Network-on-Chip design using particle swarm optimization, Journal of Experimental & Theoretical Artificial Intelligence, 31, 5, 781-799, (2019) - https://link.springer.com/chapter/10.1007/978-981-13-0761-4_108

8. P. Veda Bhanu, Pranav Venkatesh Kulkarni, Soumya J., Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement, ACM Journal on Emerging Technologies in Computing, 15, 1, 1-23, (2019) - https://dl.acm.org/doi/abs/10.1145/3269983#:~:text=Therefore%2C%20efficient%20fault%2Dtolerant%20methods,several%20benchmark%20applications%20into%20consideration.

7. Soumya J,  Niranjan Babu K, Santanu Chattopadhyay, Multi-Application Mapping onto a Switch based Reconfigurable Network-on-Chip Architecture, Journal of Circuits, Systems and Computers (JCSC), 26, 11 (2017) - https://www.worldscientific.com/doi/10.1142/S0218126617501742

6. Sandeep Dsouza, Soumya J, Santanu Chattopadhyay,  Integrated Mapping and Synthesis Techniques for Network-on-Chip Topologies with Express Channels, ACM Transactions on Architecture and Code Optimization,(TACO) 12, 4, Article 40 (2016) - https://dl.acm.org/doi/10.1145/2831233

5. Soumya J., K. Naveen Kumar, Santanu Chattopadhyay, Integrated Core Selection and Mapping for Mesh based Network-on-Chip Design with Irregular Core Sizes, Journal of Systems Architecture, 61, 9, 410-422 (2015) - https://www.sciencedirect.com/science/article/pii/S1383762115000843

4. Soumya J., Srijan Tiwary, Santanu Chattopadhyay, Area-Performance Trade-off in Floorplan Generation of Application-Specific Network-on-Chip with Soft Cores, Journal of Systems Architecture 61, 1, 1-11 (2015) - https://www.sciencedirect.com/science/article/pii/S1383762114001428

3. Soumya J., Ashish Sharma, Santanu Chattopadhyay, Multi-Application Network-on-Chip Design using Global Mapping and Local Reconfiguration, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7, 2, Article 7 (2014) - https://dl.acm.org/doi/pdf/10.1145/2556944

2. Soumya J, Santanu Chattopadhyay, Application Specific Network-on-Chip Synthesis with flexible router placement, Journal of Systems Architecture 59, 361-371 (2013) - https://www.sciencedirect.com/science/article/pii/S1383762113000945

1. Santanu Kundu,Soumya J., Santanu Chattopadhyay, Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router, Microprocessors and Microsystems - Embedded Hardware Design 36(6),471-488 (2012) - https://www.sciencedirect.com/science/article/pii/S0141933112000877

International Conferences:

27. Jitesh Choudhary, Vishesh Bindal, Soumya J, "MANA: Multi-Application Mapping onto Mesh Network-on-Chip using ANN", 26th International Symposium on VLSI Design and Test (VDAT), 2022 (Accepted)

26. Aparna Nair M K, Vishwas Vasuki Gautam, Abhishek Revinipati, Soumya J, "Implementation and Analysis of Convolution Image Filtering with RISC-V Based Architecture", 26th International Symposium on VLSI Design and Test (VDAT), 2022 (Accepted)

25. Aparna Nair M K, Police Manoj Kumar Reddy, Abijith Y.L., Venkatesh Rajagopalan, and Soumya J " Hardware Implementation of Network Interface Architecture for RISC-V based NoC-MPSoC Framework",  2022 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems (VLSID), 2022 (Accepted)

24. M. K. Aparna Nair, P. Veda Bhanu, J. Soumya and L. Reddy Cenkeramaddi " Architectural Implementation of a Reconfigurable NoC Design for Multi-Applications," 2021 24th Euromicro Conference on Digital System Design (DSD), 2021, pp. 139-142, doi: 10.1109/DSD53832.2021.00030.

23. Jitesh Choudhary, Soumya J., and Linga Reddy Cenkarmaddi " RAMAN: Reinforcement Learning Inspired Algorithm for Mapping Applications onto Mesh NoC",  23rd ACM/IEEE International Workshop on System-Level Interconnect Pathfinding(SLIP), Nov 2021 (Accepted)

22. Jagadheesh. Samala, H. Takawale, Y. Chokhani, P. V. Bhanu and Soumya J., "Fault-Tolerant Routing Algorithm for Mesh based NoC using Reinforcement Learning," 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020, pp. 1-6, doi: 10.1109/VDAT50263.2020.9190340.

21. P. Veda Bhanu, Chetan Kumar V, Soumya J. "FILA: Fault-model for Interconnection Links in Application-Specific Network-on-Chip Design", 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, SPAIN, May 17-20 (Accepted). 

20. P. Veda Bhanu, Soumya J. "Fault-Tolerant Application-Specific Network-on-Chip Design using Discrete Particle Swarm Optimization", 2019 IEEE International Conference on Industrial and Information Systems (ICIIS), Peradeniya, Sri Lanka, December 18-20, 2019 (Article in press) 

19. Joshua Pushparaj, P. Veda Bhanu, Soumya J, "A Link Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips", 2019 IEEE International Symposium on Smart Electronic Systems (iSES), Rourkela, India, December 16-18, 2019 (Article in press)

18. Divyansh Mahajan, Swarali Patil, Wagh Vipul, Mohit Dangayach, P. Veda Bhanu, and Soumya J, "Design Automation of Network-on-Chip Prototype on FPGA", 2019 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), Manipal, India, August 11-12, 2019 (Article in press) 

17. P. Veda Bhanu, S. Jagadheesh, V. Bhat, G. Agarwal and J. Soumya, "FPGA Implementation of Novel Routing Algorithm for Buttery-Fat-Tree Topology based NoC Design," 2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Lausanne, Switzerland, 2019, pp. 69-72. doi:10.1109/PRIME.2019.8787747.

16. Mohit Upadhyay, Monil Shah, P. Veda Bhanu, Soumya J., and Linga Reddy Cenkarmaddiy., "Multi-Application based Network-on-Chip Design for Mesh-of-Tree topology using Global Mapping and Reconfigurable Architecture" The 32nd International Conference on VLSI Design, New Delhi, January 2019 

15. Mohit Upadhyay, Monil Shah,P. Veda Bhanu, Soumya J.,  Linga Reddy Cenkarmaddi, and Henning Idsøe,

"A Novel Fault-Tolerant Routing Technique for Mesh-of-Tree Based Network-on-Chip Design", IEEE Region 10 International Conference (TENCON),  Jeju Island, Korea, October 2018 

14. P. Veda Bhanu, Pranav Venkatesh Kulkarni, Soumya J., Linga Reddy Cenkarmaddi, and Henning Idsøe,

 "Fault-Tolerant Network-on-Chip Design for Mesh-of-Tree Topology Using Particle Swarm Optimization", IEEE Region 10 International Conference (TENCON), Jeju Island, Korea, October 2018

13. Monil Shah, Mohit Upadhyay, Veda Bhanu P, Soumya J, and Linga Reddy Cenkeramaddi, "A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree based Network-on-Chips", Accepted in 22nd International Symposium on VLSI Design and Test (VDAT), June 2018.

12. P. Veda Bhanu, Pranav Kulkarni, Soumya J, Linga Reddy Cenkarmaddi, and Henning Idsøe, "Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement", Accepted in 14th Conference on PhD Research in Microelectronics and Electronics (PRIME), July 2018. 

11. Mohit Upadhyay, Monil Shah, P. Veda Bhanu, Soumya J, Linga Reddy Cenkeramaddi, "Fault tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration" Accepted in International Workshop on High Performance and Dynamic Reconfigurable Systems and Networks (DRSN), July 2018.

10. Divvya Sinha, Ashmita Roy, Kunchakuri Varun Kumar, Pranav Kulkarni, Soumya J, “Dn-FTR: Fault-Tolerant Routing Algorithm for Mesh based Network-on-Chip” Accepted IEEE International Conference on Recent Advances in Information Technology (RAIT), March 2018.

9. P. Veda Bhanu, Pranav Venkatesh Kulkarni, U. Anil Kumar and Soumya J, “Buttery-Fat-Tree Topology based Fault-Tolerant Network-on-Chip Design using Particle Swarm Optimization” Accepted in International Conference on Harmony search, Soft Computing and Applications (ICHSA), February 2018.

8. Parth Shah, Kanniganti Abhishek, Soumya J, Fault-Tolerant Application Specific Network-on-Chip Design, 017 7th International Symposium on Embedded Computing and System Design (ISED), Durgapur, 2017, pp. 1-5. doi: 10.1109/ISED.2017.8303920

7. Sai Anirudh, Soumya J,  Routing Algorithm for Application-Specific Network-on-Chip with Irregular Core Sizes, 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Bhopal, 2017, pp. 56-60. doi: 10.1109/iNIS.2017.21

6. Soumya J, P S Phani Teja, Flexible Spare Core Placement for Fault-Tolerant Network-on-Chip Design, Accepted in Work-In-Progress, VDAT (2017)

5. Soumya J, P S Phani Teja, Flexible Spare Core Placement for Fault-Tolerant Network-on-Chip Design, Accepted in Work-In-Progress, DAC (2017)

4. Soumya J, Santanu Chattopadhyay, Application-Specific and Reconfigurable Network-on-Chip Design, Nominated for Best PhD Thesis, VLSID (2017) 

3. Sandeep Dsouza, Soumya J, Santanu Chattopadhyay, A Constructive Heuristic for Application Mapping onto an Express Channel based Network-on-Chip,  VDAT 1-6 (2015)

2. Soumya J., Ashish Sharma, Santanu Chattopadhyay, A Locally Reconfigurable Network-on-Chip Architecture and Application Mappingonto it, VDAT 1-6 (2014)

1. Soumya J., Putta Venkatesh, Santanu Chattopadhyay, Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis, ISVLSI 2011 341-342 (2011)

Dr. Syed Ershad Ahmed

Journals: 

12.     U. Anil Kumar, Vignesh and Syed Ershad Ahmed. "Compressor based Hybrid Approximate Multiplier Architectures with Efficient Error Correction Logic," Computers and Electrical Engineering (2022). [Accepted] 

11.     U. Anil Kumar, Sahith and Syed Ershad Ahmed. "Design and Exploration of Low Power SAD Architectures using Approximate Compressors for Integer Motion Estimation," Microprocessor and Microsystem (2022). [Accepted] 

10.     U. Anil Kumar, Avinash, Vignesh, Suresh and Syed Ershad Ahmed. "CAAM: Compressor-based Adaptive Approximate Multipliers for Neural Network Applications ," IEEE Embedded Systems Letters (2022). [Accepted] 

 9.  Aroondhati, Smriti, U. Anil Kumar,  and Syed Ershad Ahmed, "A General Methodology to Optimize Flagged Constant Addition ,"Journal of Circuits, Systems and Computers (2022) [Accepted]  

8.     U. Anil Kumar, Sumit Kumar and Syed Ershad Ahmed. "Low-Power Compressor-based Approximate Multipliers with Error-Correcting Module ," IEEE Embedded Systems Letters (2021).   

 7.   Syed Ershad Ahmed and Mohan, "An Efficient Hardware Approach for Approximate Logical Computation ,"Journal of Circuits, Systems and Computers (2021) 

6.   U. Anil Kumar, Sahith, Sumit Chatterjee, and Syed Ershad Ahmed, "A High-Speed and Power-Efficient Approximate Adder for Image Processing  Applications ,"Journal of Circuits, Systems and Computers (2021). 

5.    Nambi, Suresh, U. Anil Kumar, Kavya Radhakrishnan, Mythreye Venkatesan, and Syed Ershad Ahmed. "DeBAM: Decoder Based Approximate Multiplier for Low Power Applications," IEEE Embedded Systems Letters (2020).  

4.  U. Anil Kumar and Syed Ershad Ahmed, " Hardware Efficient Approximate Multiplier Architectures for Media Processing Applications,” Circuit World.  (2021)    

3.    U. Anil Kumar and Syed Ershad Ahmed, "Compressor based Approximate Multiplier Architectures for Media Processing Applications,” International Journal of Electrical & Computer Engineering,  Vol 11, No.4, Aug 2021 

2.  Syed Ershad Ahmed and M. B. Srinivas, "An improved logarithmic multiplier for media processing." Journal of Signal Processing Systems  (2019): 561-574 

1.Syed Ershad Ahmed, Santosh Varma, and M. B. Srinivas, "Improved designs of digit-by-digit decimal multiplier." Integration 61 (2018): 150-159. 

 Book Chapter: 

1. U. Anil Kumar, and. Syed Ershad Ahmed, "A Classification and Evaluation of Approximate Multipliers," In Microelectronics and Signal Processing Advanced Concepts and Applications,1st Edition, CRC Press, Taylor & Francis (2021).

Conferences: 

2022:

11  1. Suraj, Naren, Anil Kumar and. Syed Ershad Ahmed, " Power Efficient Approximate Booth Multipliers for Error Resilient Applications”, 2022 INDICON (Accepted)

2. Anil Kumar, Sreehari and. Syed Ershad Ahmed, “Power Efficient Approximate Multiplier Architectures for Error Resilient Applications”, 2022 INDICON (Accepted)

3. Sriram, Anil Kumar and. Syed Ershad Ahmed, " Power Efficient Approximate Divider Architectures for Error Resilient Applications”, 2022 IEEE CICT Accepted)

2021:

11  1. Santhosh and. Syed Ershad Ahmed, "Design and Evaluation of Efficient Decimal Multiplier Architectures," In Soft  Computing and Signal Processing, pp. 563-571. Springer, Singapore, 2021.

2. Anil Kumar and. Syed Ershad Ahmed, "Approximate Multiplier  Architectures for Error Resilient Applications:, 2021 IEEE International Symposium on Smart Electronic Systems (Accepted)

3. Sahith, Anil Kumar and. Syed Ershad Ahmed, "Power  Efficient MLOA  for Error Resilient Applications:, 2021 IEEE International Symposium on Smart Electronic Systems (Accepted)

4.  Anil Kumar and. Syed Ershad Ahmed, "Lower part OR Based  Approximate Multiplier  for Error Resilient Applications:, 2021 IEEE International Symposium on Smart Electronic Systems (Accepted)

5.   Syed Ershad Ahmed et al. "Face Recognition and Detection using Inexact Arithmetic, 2021 IEEE ICONAT (Accepted)

2020: 

1.   1.Reddy, C. Sai Revanth, U. Anil Kumar, and Syed Ershad Ahmed, "Design of Efficient Approximate Multiplier for Image Processing Applications," In International conference on Modelling, Simulation and Intelligent Computing, pp. 511-518. Springer, Singapore, 2020.

2.   2. Alla, Navteja, and Syed Ershad Ahmed, "An Area and Delay Efficient Logarithmic Multiplier," In 2020 International Conference on Contemporary Computing and Applications (IC3A), pp. 169-174. IEEE, 2020

3.   3. Kumar, Uppugunduru Anil, Nishant Jain, Sumit K. Chatterjee, and Syed Ershad Ahmed,"Evaluation of Multiplier-Less DCT Transform Using In-Exact Computing," In International Conference on Machine Learning, Image Processing, Network Security and Data Sciences, pp. 11-23. Springer, Singapore, 2020.

4.      4. Kumar, Uppugunduru Anil, Mohammed Hamed Ahmed, and Syed Ershad Ahmed, "An Evaluation of the Canny Edge Detection Algorithm using Hybrid Approximate Adder Architecture," In 2020 IEEE-HYDCON, pp. 1-5. IEEE, 2020.

5    

2016: 

1. Syed Ershad Ahmed, Sanket Kadam, and M. B. Srinivas. "An iterative logarithmic multiplier with improved precision." 2016 IEEE 23nd Symposium on Computer Arithmetic (ARITH). IEEE, 2016.

2. Syed Ershad Ahmed, S. Sweekruth Srinivas, and M. B. Srinivas. "A Hybrid Energy Efficient Digital Comparator." 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID). IEEE, 2016.

2014: 

1. Soumya Ganguly, Abhishek Mittal, Syed Ershad Ahmed and M.B.Srinivas. "A Unified Flagged Prefix Constant Addition-Subtraction Scheme for Design of Area and Power Efficient Binary Floating-Point and Constant Integer Arithmetic Circuits." IEEE Asia Pacific Conference on Circuits and Systems(APCCAS),2014, 17-20 Nov.2014, Ishigaki Island, Okinawa, Japan.

2. Varma, Ch, Syed Ershad Ahmed and M. B. Srinivas. "A Decimal/Binary Multi-operand Adder Using aFast Binary to Decimal Converter." VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on. IEEE, 2014.

 2013: 

1.  K.V.S.Sashank , Syed Ershad Ahmed , " A Reconfigurable Fixed Width Scheme for Recursive Multipliers”, Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2013 , 19-21 Dec. 2013.

2. Syed Ershad Ahmed and M.B.Srinivas , "Design of Low Power MAC unit in High Performance DSP Systems, “21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) , proceedings., 7-9 October 2013, Istanbul ,Turkey.

3. Syed Ershad Ahmed, Pawan Sastry, Sreehari Veeramanchaneni, M.B.Srinivas;, " A High Accuracy, Low Memory Logarithmic Converter “,Fourth International Symposium Highly-Efficient Accelerators and Reconfigurable Technologies (HEART) , conference proceedings., pp.121-124, 13-14 June 2013,Edinburgh ,Scotland.

 2012: 

1.Ganguly, Soumya, Abhishek Mittal, and Syed Ershad Ahmed, "A Reconfigurable Parallel Prefix Ling Adder with modified Enhanced Flagged Binary logic." Microelectronics and Electronics (PrimeAsia), 2012 Asia Pacific Conference on Postgraduate Research in. IEEE, 2012.

2.Vudadha, Chetan, Syed Ershad Ahmed et al. "Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders." 2012 IEEE Computer Society Annual Symposium on VLSI. IEEE, 2012.

3. Vudadha, Chetan, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, and M. B. Srinivas. "Low-power self reconfigurable multiplexer based decoder for adaptive resolution flash adcs." In 2012 25th International Conference on VLSI Design, pp. 280-285. IEEE, 2012.

4.6.Ahmed, Syed Ershad, Sibi Abraham, Sreehari Veeramanchaneni, and M. B. Srinivas. "A modified twin precision multiplier with 2D bypassing technique." In 2012 International Symposium on Electronic System Design (ISED), pp. 102-106. IEEE, 2012.

 2011: 

 1. Kumar, V. Chetan, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, and M. B. Srinivas. "A unified architecture for BCD and binary adder/subtractor." In 2011 14th Euromicro Conference on Digital System Design, pp. 426-429. IEEE, 2011.

2.Kumar, V. Chetan, P. Sai Phaneendra, Syed Ershad Ahmed, V. Sreehari, N. Moorthy Muthukrishnan, and M. B. Srinivas. "A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block." In 2011 International Symposium on Electronic System Design, pp. 100-105. IEEE, 2011.

3.Kumar, Chetan, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, and M. B. Srinivas. "A prefix based reconfigurable adder." In 2011 IEEE Computer Society Annual Symposium on VLSI, pp. 349-350. IEEE, 2011.

Dr. Sayan Kanungo

Journal Publications

(Before Joining BITS-Pilani)

1.      S. Kanungo, S. Chattopadhyay, P.S. Gupta, and H. Rahaman, “Comparative Performance Analysis of the Dielectrically Modulated Full- Gate and Short-Gate Tunnel FET-Based Biosensors,” IEEE Trans. on Electron Device, Vol. 62, Issue. 3, pp. 994 - 1001 (2015). Doi: 10.1109/TED.2015.2390774. [SCI, 2015 Impact Factor: 2.21]

2.      S. Kanungo, S. Chattopadhyay, P.S. Gupta, K. Sinha, and H. Rahaman, “Study and Analysis of the Effects of SiGe Source and Pocket Doped Channel on Sensing Performance of Dielectrically-Modulated Tunnel FET based Bio-Sensors,” IEEE Trans. on Electron Device, Vol. 63, Issue. 6, pp. 2589 - 2596 (2016). Doi: 10.1109/TED.2016.2556081. [SCI, 2016 Impact Factor: 2.61]

3.      S. Kanungo, S. Chattopadhyay, K. Sinha, P.S. Gupta, and H. Rahaman, “A Device Simulation based Investigation on Dielectrically Modulated Fringing Field Effect Transistor for Biosensing Applications,” IEEE Sensors Journal, Vol. 17, Issue. 5, pp. 1399 - 1406 (2016). Doi: 10.1109/JSEN.2016.2633621. [SCI, 2016 Impact Factor: 2.51]

4.      S. Kanungo, S. A. Mondal, S. Chattopadhyay, and H. Rahaman, “Design and Investigation on Bio-Inverter and Bio-Ring-oscillator for Dielectrically Modulated Biosensing Applications,” IEEE Trans. on Nanotechnology, Vol. 16, No. 6,pp. 974 - 981 (2017). Doi: 10.1109/TNANO.2017.2736161. [SCI, 2017 Impact Factor: 2.86] 

(After Joining BITS-Pilani)

1.      S. Sharma, S. K. Ganeshan, P. K. Pattnaik, S. Kanungo, and K. N. Chappanda, “Laser induced flexible graphene electrodes for electrochemical sensing of hydrazine,” Materials Letters, Vol. 262, pp. 127150 (2019). Doi: 10.1016/j.matlet.2019.127150. [SCI, 2019 Impact Factor: 3.20]

2.      P. M. P. Raj, V J. Louis, S. K. Chatterjee, S. Kanungo, and S. Kundu, “Ferroelectric Memristive Networks for Dimensionality Reduction: A Process for Effectively Classifying Cancer Datasets,” Integrated Ferroelectrics, Vol. 201, Issue.1, pp. 126-141 (2019). Doi: 10.1080/10584587.2019.1668697. [SCI, 2019 Impact Factor: 0.56]

3.      D. Som, B. Majumdar, S. Kundu, and S. Kanungo*. "Investigation of Charge Plasma Enhanced Tunnel Field Effect Transistor for Hydrogen Gas Sensing Application ". IEEE Sensors Letter, Vol. 4, Issue. 6 (2020). Doi: 10.1109/LSENS.2020.2988589. [SCI, 2020 Impact Factor: Not Assigned] (*Corresponding Author)

4.      S. Kanungo*,  B. Majumdar, S. Mukhopadhyay, D. Som, S. Chattopadhyay, and H. Rahaman. "Investigation on the Effects of Substrate, Back-Gate Bias and Front-Gate Engineering on the Performance of DMTFET based Biosensors". IEEE Sensors Journal, Vol. 20, Issue. 18, pp. 10405-10414 (2020). Doi: 10.1109/JSEN.2020.2994295. [SCI, 2020 Impact Factor: 3.07] (*Corresponding Author)

5.      P. K. R. Boppidi, P. Joshna, D. Som, H. Renuka, P. Biswas, D. Bhattacharyya, S. Kanungo, S. Banerjee, and S. Kundu, “Understanding the Efficacy of Cu in creating Oxygen Vacancies and Temperature Dependent Electrical Transport in Solution Processed Cu: ZnO Thin Films”, Materials Science in Semiconductor Processing, Vol.120, pp. 105331, (2020). Doi: 10.1016/j.mssp.2020.105311. [SCI, 2020 Impact Factor: 3.09]

6.      A. Mukhopadhyay, S. Kanungo, and H. Rahaman "Effect of Stacking Arrangement on Device Behavior of Bilayer MoS2 FETs". Journal of Computational Electronics, Vol.20, pp. 161-168 (2021). Doi: 10.1007/s10825-020-01636-w. [SCI, 2020 Impact Factor: 1.81]

7.      V. Selamneni, S. Kanungo, and P. Sahatya "Large area growth of SnS2/Graphene on cellulose paper as a flexible broadband photodetector and investigating the band structure through First Principle Calculations". RSC Materials Advances, Vol.2, pp. 2373-2381, (2021). Doi: 10.1039/D1MA00054C. [SCI, 2021 Impact Factor: Not Assigned]

8.      N. Bokka, D. Som, S. Kanungo, and P. Sahatya "Investigation of the Transduction Mechanism of Few Layer SnS2 for pressure and strain sensing: Experimental correlation with First Principles Study". IEEE Sensors Journal, Vol.21, Issue.15, pp.17254-17261 (2021). Doi: 10.1109/JSEN.2021.3082429. [SCI, 2021 Impact Factor: 3.30]

9.      S. Jana Mukhopadhyay, B. Mazumdar, K. N. Chappanda, S. C. Mukhopadhyay, and S. Kanungo* "Performance Analysis of the Diagonal Tunneling based Dielectrically Modulated Tunnel FET for Label-free Bio-sensing Applications". IEEE Sensors Journal, Vol.21, Issue.19, pp.21643-21652 (2021). Doi: 10.1109/JSEN.2021.3103998.  [SCI, 2021 Impact Factor: 3.30] (*Corresponding Author)

10.   P. Joshna, A. Tiwari, S. Kundu, P. Sahatya, and S. Kanungo* "Effects of Artificial Stacking Configurations and Biaxial Strain on the Structural, Electronic and Transport Properties of Bilayer GaSe- A First Principle Study". Materials Science in Semiconductor Processing, Vol.137, pp. 106236 (2022).  Doi: 10.1016/j.mssp.2021.106236. [SCI, 2022 Impact Factor: 4.64] (*Corresponding Author)

11.   N. Bokka, V. Adepu, A. Tiwari, S. Kanungo, and P. Sahatya "A Detailed Comparative Performance Analysis of the Transition Metal Di-chalcogenides (TMDs) based Strain Sensors through Experimental Realisations and First Principle Calculations". FlatChem, Vol.32, 100344 (2022). Doi: 10.1016/j.flatc.2022.100344.  [SCI, 2022 Impact Factor: 5.83]

12.   S. Tayal, B. Mazumdar, S. Bhattacharya, and S. Kanungo* "Performance Analysis of the Dielectrically Modulated Junction Less Nanotube Field Effect Transistor for Biomolecule Detection". IEEE Transactions on NanoBio Science, Accepted in Press (2022). Doi: 10.1109/TNB.2022.3172702.  [SCI, 2022 Impact Factor: 3.21] (*Corresponding Author)

13.   A. Tiwari, P. Joshna, A. Choudhury, S. Bhattacharya, and S. Kanungo* "Theoretical Analysis of the NH3, NO, and NO2 Adsorption on Boron-Nitrogen and Boron-Phosphorous Co-doped Monolayer Graphene - A Comparative Study". FlatChem, Vol.34, 100392 (2022). Doi: 10.1016/j.flatc.2022.100392. [SCI, 2022 Impact Factor: 5.83] (*Corresponding Author)

14.   P. Joshna, P. P. Anand, P. Parshi, V. Jain, A. Tiwari, S. Bhattacharya, S. Chakraborty, and S. Kanungo* "Comparative Analysis of Strain Engineering on the Electronic Properties of Homogenous and Heterostructure Bilayers of MoX2 (X=S, Se, Te)". Micro and Nanostructures, Vol.168, 207334 (2022). Doi: 10.1016/j.micrna.2022.207334. [SCI, 2021 Impact Factor: 3.22] (*Corresponding Author)

15.   S. Bhattacharya, S. Das, S. Tayal, J. Ajayan, L. M. I. L. Joseph, T. K. Juluru, A. Mukhopadhyay, S. Kanungo, D. Das, and S. Rebelli "Minimization of Crosstalk Noise and Delay Using Reduced Graphene Nano Ribbon (GNR) Interconnect". Microelectronics Journal, Vol.127, 105533 (2022). Doi: 10.1016/j.mejo.2022.105533. [SCI, 2022 Impact Factor: 1.99]

16.   S. Payra, S. Kanungo, and S. Roy "Controlling C-C coupling in Electrocatalytic Reduction of CO2 over Cu1-xZnx/C". Nanoscale, Vol.14, 13352-13361 (2022). Doi: 10.1039/D2NR03634G. [SCI, 2022 Impact Factor: 8.31]

17.   S. Kanungo, A. Bhattacharjee, N. Bahadursha, and A. Ghosh "Comparative Analysis of LiMPO4 (M= Fe, Co, Cr, Mn, V) as Cathode Materials for Lithium-ion Battery Applications- A First Principle-based Theoretical Approach". MDPI nanomaterials, Vol. 12(19), 3266 (2022). Doi: 10.3390/nano12193266. [SCI, 2021 Impact Factor: 5.72]

18.   A. Tiwari,  N, Bahadursha, P. Joshna, S. Chakraborty, and S. Kanungo* "Comparative Analysis of Boron, Nitrogen, and Phosphorous Doping in Monolayer of Semi-metallic Xenes (Graphene, Silicene, and Germanene) - A First Principle Calculation based Approach". Materials Science in Semiconductor Processing, Vol. 153, 107121 (2023). Doi: 10.1016/j.mssp.2022.107121. [SCI, 2022 Impact Factor: 4.64] (*Corresponding Author)

19.   S. Kanungo*, G. Ahmad, P. Sahatiya, A. Mukhopadhyay, and S. Chattopadhyay "2D Materials-Based Nanoscale Tunneling Field Effect Transistors: current developments and future prospects". npj 2D Materials and Applications, Vol. 6(83), 1-29 (2022). Doi: 10.1038/s41699-022-00352-2 [SCI, 2020 Impact Factor: 11.11] (*Corresponding Author) 

20. P. Joshna, S. Patel, S. Sinha, R. K. Maliidi, G. V. N. Karthik, B. Mazumdar, S. C. Mukhopadhyay, and S. Kanungo* "Investigation of Dielectrically Modulated Electron Hole Bilayer Tunnel Field Effect Transistor for Biomolecule Detection". Current Applied Physics, Vol.47, 60-71 (2023). Doi: 10.1016/j.cap.2023.01.001 [SCI, 2021 Impact Factor: 2.86] (*Corresponding Author)

21.      N. Bahadursha, A. Tiwari, S. Chakraborty, and S. Kanungo*, “Theoretical Investigation of the Structural and Electronic Properties of Bilayer Van der Waals Heterostructure of Janus Molybdenum Di-Chalcogenides- Effects of Interlayer Chalcogen Pairing,” Materials Chemistry and Physics, Vol. 297, 127397 (2023). Doi: 10.1016/j.matchemphys.2023.127375 [SCI, 2022 Impact Factor: 4.78] (*Corresponding Author)

22.      G. Polumati, A. Tiwari, C. S. Reddi Kolli, S. Kanungo, A. De L. Bugallo, P. Sahatiya “CVD Grown MoS2 Monolayer Based Ultra-Sensitive Human Breath Sensors: Experimental and Theoretical Study,” IEEE Sensors Letters, Vol.7 (2), pp. 1-10 (2023). Doi:10.1109/LSEN.2023.3241329  [SCI, 2022 Impact Factor: Not Assigned]  

23.   V. Adepu, M. Tachacharya, R.S. Fernandes, A. Tiwari, S. Kanungo*, N. Dey*, P. Sahatiya* “Perylene Diimide (PDI) based Flexible Multifunctional Sensor Design for Personal Healthcare Monitoring- A Complementary Approach Involving Experimental and Theoretical Investigation,” Advanced Materials Technologies, Accepted, In-Press (2023). Doi:10.1002/admt.202201633  [SCI, 2022 Impact Factor: 8.856] (*Co-Corresponding Author)

Book-Chapter Publications

(After Joining BITS-Pilani)

1.      D. Som, A. Paul, Tanu, A. Mukhopadhyay, N. Thakur and S. Kanungo*, “First Principle Calculation Based Investigation on the Two Dimensional Sandwiched Tri-layer Van der Waals Hetero-structures of MoSe2 and SnS2”, N. Goel et al. (eds.), Modelling, Simulation and Intelligent Computing, Lecture notes in Electrical Engineering (Springer), 659, pp. 40-47 (2020).  Doi: 10.1007/978-981-15-4775-1_5. (*Corresponding Author)

2.      D. Som, A. Paul, Tanu, A. Mukhopadhyay, N. Thakur and S. Kanungo*, “Van der Waals Hetero-structures based on Transition Metal Di-Chalcogenides- Current Status and Prospects in Broad-Band Photo-detector Applications”, S. Goel et al. (eds.), Microelectronics and Signal Processing: Advanced Concepts and Applications, (Taylor & Francis), 1st Edition, pp. 16-31 (2021).  Doi: 10.1201/9781003168225-1. (*Corresponding Author)

3.     S. J. Mukhopadhyay, S. Kanungo, V. Maheshwari, M. Mitra, “Terahertz IMPATT Sources Based on Silicon Carbide”, A. Acharyya et al. (eds.), Advanced Materials for Future Terahertz Devices, Circuits and Systems , (Springer), Early Access (2021).  Doi: 10.1007/978-981-33-4489-1_5.

4.     S. J. Mukhopadhyay, S. Kanungo, A. Acharyya, M. Mitra, “Gallium Oxide-Based IMPATT Sources for THz Applications”, A. Acharyya et al. (eds.), Generation, Detection and Processing of Terahertz Signals, (Springer), Early Access (2021).  Doi: 10.1007/978-981-16-4947-9_6. 

5.      A. Tiwari, S. J. Mukhopadhyay, and S. Kanungo*, “Nanomaterials For Next Generation Interconnect”, S. Bhattacharya et al. (eds.), Nano Interconnect Materials and Models for Next generation Integrated Circuit Design (Taylor and Francis), Accepted, In-Press (2022). Doi: . (*Corresponding Author)

6.      A. Tiwari, S. J. Mukhopadhyay, and S. Kanungo*, “The Emerging Nanostructures for Dielectrically Modulated Bio-sensing Applications- Review of Present Developments”, S. Gole et al. (eds.), Miniaturized Electrochemical Devices Advanced Concepts, Fabrications and Applications (Taylor and Francis), Accepted, In-Press (2022). Doi: . (*Corresponding Author)

International Conference Publications

(Before Joining BITS-Pilani)

1.      S. Kanungo, P.S. Gupta, H. Rahaman and PS Dasgupta “A Simple Analytical Model of Silicon On Insulator Tunnel FET,” 5th International Conference on Computers and Devices for Communication, Kolkata, India, Dec. 16-18, (2012). Doi: 10.1109/CODEC.2012.6509256.

2.      S. Kanungo, P.S. Gupta, H. Rahaman and PS Dasgupta “A detail simulation study on Extended Source Ultra-Thin Body Double-Gated Tunnel FET,” 5th International Conference on Computers and Devices for Communication, Kolkata, India, Dec. 16-18, (2012). Doi: 10.1109/CODEC.2012.6509242.

3.      S. Kanungo, P.S. Gupta, H. Rahaman and PS Dasgupta “Effects of Germanium mole fraction variation at the source of a dielectrically modulated Tunneling FET based biosensor,” 2nd International Conference on Devices Circuits and Systems, Coimbatore, India, Mar. 6-8, (2014). Doi: 10.1109/ICDCSyst.2014.6926218.

4.      S. Kanungo, S. Chattopadhyay and H. Rahaman, “Investigating the performance of Short Gate Insulator Less Dielectrically Modulated Tunnel Field Effect Transistor based Bio-Sensors,” 6th International Conference on Computers and Devices for Communication, Kolkata, India, Dec. 16-18, (2015). Doi: 10.1109/CODEC.2015.7893189.

5.      S. Kanungo, “Introduction to Dielectrically Modulated Biological Field Effect Transistor”, in proceedings of International Symposium on Devices, Circuits and Systems, March. 29-31 Kolkata, India (2018). Doi: 10.1109/ISDCS.2018.8379627. 

(After Joining BITS-Pilani)

1.      P. Anand P, P. Parshi, V. Jain, S. Bhattacharya, A. Mukhopadhyay, S. Kanungo, “A First Principle Based Investigation on the Effects of Stacking Configuration and Biaxial Strain on the Electronic Properties of Bilayer MoS2”, in proceedings of International Symposium on Devices, Circuits and Systems, March. 3-5 Hiroshima, Japan (2021). Doi: 10.1109/ISDCS52006.2021.9397905. 

2.      A. Tiwari, N. Bahadursha, J. Palepu, S. Kanungo, “Analysis of SO Adsorption on Boron-Arsenic Co-doped Monolayer Graphene- A First Principle Study ”, in proceedings of International Symposium on Devices, Circuits and Systems, March. 29-31, Kolkata, India (2022). Accepted In-Press. 

3.      A. Tiwari, N. Bahadursha, S. Bhattacharya, S. Kanungo, “Analysis of NH3 Adsorption on Boron, Nitrogen, and Phosphorus Arsenic Doped Monolayer Silicene- A First Principle Study ”, in proceedings of 15th International Conference of Sensing Technology, December. 5-7, Sydney, Australia (2022). Accepted In-Press. 

4.      N. Weeranthunge, S. Chakraborty, S. Kanungo, S. J Mahon, “Design of Compact Power Divider MMIC Applications Using Periodically Loaded Slow Wave Structure and MIM Capacitive Loading ”, in proceedings of IEEE Microwave, Antennas and Propagation Conference, December. 12-16, Bangalore, India (2022) Doi: 10.1109/MAPCON56O11.2022.10047258. 

5.      Q. T. Chau, S. Chakraborty, A. Jones, N. Weeranthunge, S. Kanungo, M. Gorman, “A Ku-band Low Noise Amplifier Implemented in 0.15 µm Gallium Arsenide p-HEMT Process ”, in proceedings of IEEE Microwave, Antennas and Propagation Conference, December. 12-16, Bangalore, India (2022) Doi: 10.1109/MAPCON56O11.2022.10047620. 

Dr. Chetan Kumar Vudadha 

Book Chapter

1. Chetan Vudadha and M. B. Srinivas (2018), "Design of Ternary Logic Circuits Using CNFETs" In “Nanoscale Devices: Physics, Modeling, and Their Application” by Kaushik, B. Boca Raton: CRC Press, https://doi.org/10.1201/9781315163116

Journal Publications

7. S. Gadgil and C. Vudadha, "Novel Design Methodologies for CNFET-Based Ternary Sequential Logic Circuits," in IEEE Transactions on Nanotechnology, vol. 21, pp. 289-298, 2022, DOI: 10.1109/TNANO.2022.3184759. [SCI and Scopus Indexed; IF: 2.967]

6. Sai Phaneendra, P., Vudadha, C. & Srinivas, M.B. "Optimization of Reversible Circuits Using Gate Pair Classification". SN COMPUT. SCI. 3, 40 (2022). DOI: 10.1007/s42979-021-00900-5. [Scopus Indexed; IF: NA]

5. S. Gadgil and C. Vudadha, "Design of CNTFET-Based Ternary ALU Using 2:1 Multiplexer Based Approach," in IEEE Transactions on Nanotechnology, vol. 19, pp. 661-671, Aug. 2020, DOI:  10.1109/TNANO.2020.3018867. [SCI and Scopus Indexed; IF: 2.967]

4.    Chetan Vudadha, Ajay Surya K, Saurabh Agrawal and M.B. Srinivas "Synthesis of Ternary Logic Circuits using 2:1 Multiplexers," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 12, pp. 4313-4325, Dec. 2018. DOI: 10.1109/TCSI.2018.2838258. [SCI and Scopus Indexed; IF: 4.14]

3.  Chetan Vudadha and M.B. Srinivas "Design of High Speed and Power Efficient Ternary Prefix Adders using CNFETs," in IEEE Transactions on Nanotechnology, vol. 17, no. 4, pp. 772-782, July 2018. DOI: 10.1109/TNANO.2018.2832649. [SCI and Scopus Indexed; IF: 2.967]

2. Chetan Vudadha, P. S. Phaneendra and M. B. Srinivas “Energy Efficient Design of CNFET-based Multi-Digit Ternary Adders," Microelectronics Journal (Elsevier), Volume 75, pp. 75-86, May 2018. DOI:10.1016/j.mejo.2018.02.004. [SCI and Scopus Indexed; IF: 1.992]

1. C. Vudadha, S. Rajagopalan, A. Dusi, P. S. Phaneendra and M. B. Srinivas, "Encoder-Based Optimization of CNFET-Based Ternary Logic Circuits," in IEEE Transactions on Nanotechnology, vol. 17, no. 2, pp. 299-310, March 2018.  DOI: 10.1109/TNANO.2018.2800015. [SCI and Scopus Indexed; IF: 2.967]
 

Conference Publications

26. S. T, S. Gadgil and C. Vudadha, "Design of CNTFET-based Ternary Logic circuits using Low power Encoder," 2022 IEEE International Symposium on Smart Electronic Systems (iSES), Warangal, India, 2022, pp. 142-147.

25. S. V. Bharadwaj and C. K. Vudadha, "Evaluation of x86 and ARM architectures using compute-intensive workloads," 2022 IEEE International Symposium on Smart Electronic Systems (iSES), Warangal, India, 2022, pp. 586-589.

24. S. Gadgil and C. Vudadha, "Design of CNFET-based Low-Power Ternary Sequential Logic circuits," 2021 IEEE 21st International Conference on Nanotechnology (NANO), 2021, pp. 169-172.

23. P. V. Bhanu, C. Vudadha and J. Soumya, "FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 2020, pp. 1-5.

22. Harita Sirugudi, Sharvani Gadgil and Chetan Vudadha, "A Novel Low Power Ternary Multiplier Design using CNFETs," 2020 33rd International Conference on VLSI Design and 18th International Conference on Embedded Systems (VLSID), Bangalore, 2020

21. P. Patel, N. Doddapaneni, S. Gadgil, and C. Vudadha, " Design of Area Optimised, Energy efficient Quaternary Circuits using CNTFETs," 2019 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), Rourkela, India, 2019,

20. C. K. Vudadha and M.B. Srinivas, "Design Methodologies for Ternary Logic Circuits," 2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL), Linz, 2018, pp. 192-197.

19. Parlapalli, Sai Phaneendra; Vudadha, Chetan and Srinivas, M. B., "An ESOP Based Cube Decomposition Technique for Reversible Circuits", Reversible Computation, Springer International Publishing (2017), 127--140.

18. Parlapalli, Sai Phaneendra; Vudadha, Chetan and Srinivas, M. B., "Optimizing the Reversible Circuits Using Complementary Control Line Transformation", Reversible Computation, Springer International Publishing (2017), 111--126.

17. C. Vudadha, P. S. Phaneendra and M. B. Srinivas, "An Efficient Design Methodology for CNFET Based Ternary Logic Circuits," 2016 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Gwalior, 2016, pp. 278-283.

16. Pal, Subhankar; Vudadha, Chetan; Phaneendra, P.Sai; Veeramachaneni, Sreehari; M.B. Srinivas, "A New Design of an N-Bit Reversible Arithmetic Logic Unit," in Fifth International Symposium on Electronic System Design (ISED), 2014  , vol., no., pp.224-225, 15-17 Dec. 2014.

15. Phaneendra, P.S.; Vudadha, C.; Sreehari, V.; Srinivas, M.B., "An Optimized Design of Reversible Quantum Comparator," 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 , vol., no., pp.557,562, 5-9 Jan. 2014.

14. Vudadha, C.; Katragadda, S.; Phaneendra, P.S., "2:1 Multiplexer based design for ternary logic circuits," IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2013 , vol., no., pp.46,51, 19-21 Dec. 2013

13. Vudadha, Chetan; Sai, Phaneendra P; Sreehari, V; Srinivas, M B;,"CNFET based ternary magnitude comparator," International Symposium on Communications and Information Technologies (ISCIT),2012, vol., no., pp.942-946, 2-5 Oct. 2012.

12. Vudadha, Chetan; Phaneendra, P. Sai; Sreehari, V.; Ahmed, Syed Ershad; Muthukrishnan, N. Moorthy; Srinivas, M.B.; , "Design of Prefix-Based Optimal Reversible Comparator," IEEE Computer Society Annual Symposium on VLSI (ISVLSI),2012, vol., no., pp.201-206, 19-21 Aug. 2012.

11. Vudadha, Chetan; Phaneendra, P. Sai; Sreehari, V.; Ahmed, Syed Ershad; Muthukrishnan, N. Moorthy; Srinivas, M.B.; , "Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders," IEEE Computer Society Annual Symposium on VLSI (ISVLSI),2012, vol., no., pp.225-230, 19-21 Aug. 2012.

10. Vudadha, Chetan; Sreehari, V.; Srinivas, M. B.; , "Multiplexer Based Design for Ternary Logic Circuits," ,2012 8th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), vol., no., pp.1-4, 12-15 June 2012.

09. Vudadha, C.; Phaneendra P, S.; Makkena, G.; Sreehari, V.; Muthukrishnan, N.M.; Srinivas, M.B.; , "Design of CNFET based ternary comparator using grouping logic," 2012 IEEE Faible Tension Faible Consommation (FTFC),, vol., no., pp.1-4, 6-8 June 2012.

08. Vudadha, C.; Makkena, G.; Nayudu, M.V.S.; Phaneendra, P.S.; Ahmed, S.E.; Veeramachaneni, S.; Muthukrishnan, N.M.; Srinivas, M.B.; , "Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs," 2012 25th International Conference on VLSI Design (VLSID), , vol., no., pp.280-285, 7-11 Jan. 2012.

07. Kumar, V. Chetan; Phaneendra, P. Sai; Ahmed, Syed Ershad; Sreehari, V.; Muthukrishnan, N. Moorthy; Srinivas, M.B.;, "A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block,"International Symposium on Electronic System Design (ISED), 2011, vol., no., pp.100-105, 19-21 Dec. 2011.

06. Chetan Kumar, V; Sai Phaneendra, P; Ershad Ahmed, S; Sreehari, V; Moorthy Muthukrishnan, N; Srinivas, M.B.; , "Higher radix sparse-2 adders with improved grouping technique," TENCON 2011 - 2011 IEEE Region 10 Conference , vol., no., pp.676-679, 21-24 Nov. 2011.

05. Phaneendra, P.S.; Vudadha, C.; Ahmed, S.E.; Sreehari, V.; Muthukrishnan, N.M.; Srinivas, M.B.; , "Increment/decrement/2's complement/priority encoder circuit for varying operand lengths," 11th International Symposium on Communications and Information Technologies (ISCIT), 2011 , vol., no., pp.472-477, 12-14 Oct. 2011.

04. Vudadha, C.; Veeramachaneni, S.; Srinivas, M.B.; "Non-linear partitioning for decimal logarithm approximation," Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2011 , vol., no., pp.102-105, 6-7 Oct. 2011.

03. Chetan Kumar, V.; Sai Phaneendra, P.; Ershad Ahmed, S.; Veeramachaneni, S.; Moorthy Muthukrishnan, N.; Srinivas, M.B.; , "A Prefix Based Reconfigurable Adder," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2011, vol., no., pp.349-350, 4-6 July 2011.

02. Chetan Kumar, V.; Sai Phaneendra, P.; Ahmed, S.E.; Veeramachaneni, S.; Moorthy Muthukrishnan, N.; Srinivas, M.B.; , "A Unified Architecture for BCD and Binary Adder/Subtractor," 14th Euromicro Conference on Digital System Design (DSD), 2011, vol., no., pp.426-429, Aug. 31 2011-Sept. 2 2011.

01. Chetan Vudadha, Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, Moorthy Muthukrishnan and Srinivas M.B “An Improved Sum Computation Block for adders with High Sparseness ", in 20th International Workshop on Logic & Synthesis (IWLS 2011), June 2011, San Diego, CA, USA.

Dr. Parikshit Sahatiya

JOURNALS

79.  Navven Bokka., Sahatiya, P*. "Heat and Light Triggered Mechanical Destruction of 2d Materials Based Electronic Devices Fabricated on Wax Substrate". FlatChem (Accepted Manuscript).

78. Soumi Saha ., Vivek Adepu ., Khush Gohel ., Sahatiya, P*., and Surya Shankar Dan*., "Demonstration of a 2D SnS/MXene Nanohybrid Asymmetric Memristor",  IEEE Transactions on Electron Devices  (Accepted Manuscript).

77.  Venkatarao Selamneni., Abhishek Mukherjee., Harini Raghavan., Gomathi P. Thanga., Chandra Sekhar Reddy Kolli., Subhradeep Pal., Arnab Hazra., Sahatiya, P*., "Plasmonic Au Nanoparticles Coated on ReS2 Nanosheets for Visible-NIR Photodetector", ACS Applied Nano Materials (Accepted Manuscript).

76. Venkatarao Selamneni., Sukruth S., Sahatiya, P*., Performance Enhancement of Highly Flexible SnS(p)/MoS2(n) Heterostructure based Broadband Photodetector by Piezo-phototronic Effect FlatChem. 2022 (Accepted Manuscript).

75. Adepu, V., Kunchur, A.,  Chandrasekhar Reddy K., Sukruth S., Mattela, V., Sahatiya, P*., High-Performance Visible Photodetector Based on 1D SnO2 Nanofibers with Ti3C2Tx (MXene) Electron Transport Layer. ACS Applied Nanomaterials. 2022 (Accepted Manuscript).

74. Battina, S.,  Adepu, V.,  Sahatiya, P., Nandi, S.*  An MXene Based Flexible Patch Antenna for Pressure and Level Sensing Applications. FlatChem. 2022 (Accepted Manuscript).

73. Selameni., V., Adepu, V., Raghavan, H., Sahatiya, P*. Ultra-high Responsivity and Enhanced Trap Assisted Charge Transfer by utilizing Ti3C2Tx (MXene) as Transport Layer for ReS2 based Flexible Broadband Photodetector: A Better Alternative to Graphene. FlatChem. 2022 (Accepted Mansucript) 

72.  Chandrasekhar Reddy K., Venkatarao Selamneni, Barbara A., Muniz Martinez., Andres Fest C., David Emanuel Sanchez, Mauricio Terrones., Elodie S., Andres De Luna Bugallo*, Parikshit Sahatiya*. Broadband, Ultrahigh Resposive Monolayer MoS2/SnS2 Qunatum Dot based Mixed Dimensional Photodetector. ACS Applied Materials and Interfaces. 2022 (Accepted Manuscript)

71. Adepu, V., Kunchur, A., Tathacharya, M., Mattela, V., Sahatiya, P*., SnS/TiC2Tx (MXene) Nanohybrid Based Electromechanical Sensors for Sign to Text Translation and Posture Analysis. ACS Applied Electronic Materials. 2022 (Accepted Manuscript)

70. Bokka, N., Adepu, V., Tiwari, A., Kanungo, S., Sahatiya, P*. A Detailed Comparitive Performance Analysis of the Transistion Metal Di-chalcogenides (TMDs) based Strain Sensors through Experimental Realisations and First Principle Calculations. FlatChem, 2022 (Accepted Manuscript)

69. Kumar, M., Kumari, P*., Sahatiya, P. P)VDF-TrFE)/Zno nanofiber Composite based Nanogenerator as Self-Powered Sensor: Fabrication and Characterization. Journal of Polymer Research, 2022 (Accepted Manuscript)

68. Bokka, N., Adepu, V., Sahatiya, P*. Sublimation of MXene/Camphor Device: A study on self-destructive dry transiency. Materials Advances, 2022 (Accepted Manuscript)

67. Adepu, V., Kamath, K., Sukruth S., Sahatiya, P*. MXene/TMDs nanohybrid for the development of smart electronic textiles based on  physical electromechanical sensors. Advanced Materials Interfaces, 2021. (Accepted Manuscript)

66. Joshna, P., Tiwari, A., Sahatiya, P., Kundu, S., Kanungo, S. Effect of artificial stacking configurations and biaxial strain on the structural, electronic and transport properties of bilayer GaSe - A first principle study. Material Science in Semiconductor Processing, 2021. (Accepted Manuscript)

65. Selamneni, V, Pranav, A., Singh, A., Sahatiya, P*. Hybrid 0D-2D WS2 QDs (n)/SnS (p) as Distributed Heterojunctions for Highly Responsive Flexible Broadband Photodetector. ACS Applied Electronic Materials, 2021 (accepted manuscript)  

64. Bokka, N., Gohel, K., Sahatiya, P*.A water soluble micropatterned MoS2 QDs/PVA Film as as Transient Contact Pressure) and Non-contact (Humidity) as Touch and Proximity Sensor. Journal of Applied Polymer Science, 2021 (Accepted manuscript)

63. Kamath, K., Adepu, V., Mattela V and Sahatiya, P*. Ti3C2Tx/MoS2xSe2(1-x) nanohybrid multilayer structures for piezoresistive mechanical transduction. ACS Applied Electronic Materials, 2021 (Accepted Manuscript)

 62. Amogh BS, Selamneni V, Bokka, N., Sahatiya, P*. Remarkably Stable Black Phosphorous Quantum Dots - Polyvinyl Alcohol Film as Water Soluble Breath Sensor. IEEE Transactions on Electron Devices, 2021 (accepted manuscript)

61. K. Chandra Sekhar Reddy, Venkatarao Selamneni, M.G. Syamala Rao, J. Meza-Arroyo, R. Ramirez-Bon*, Parikshit Sahatiya*.  All Solution Processed p-NiO/p-CdS Flexible Rectifying Junction: Applications Towards Broadband Photodetector and Human Breath Monitoring. Applied Surface Science, 2021 (Accepted Manuscript)

60. Bokka, N., Karhade, J., Sahatiya, P*. Deep Learning Enabled Classification of Real Time Respiration Signals Acquired by MoSSe Quantum Dots based Flexible Sensor. Journal of Materials Chemistry B, 2021. (Accepted Manuscript) 

59. Selemeni, V., Akshaya, T., Adepu, V., Sahatiya, P*. Laser Assisted Micropyramid patterned PDMS Encapsulation of 1D Tellurium Nanowires on Cellulose Paper for Highly Sensitive Strain Sensor and its Photodetection Studies. Nanotechnology, 2021 (Accepted Manuscript) 

58. Adepu, V., Kamath, K, Mattela, V and Sahatiya, P*. Development of Ti3C2Tx/NiSe2 nanohybrid based large area pressure sensor for unobtrusive sleep monitoring. Advanced Materials Interfaces, 2021 (Accepted Manuscript)

57. Bokka, N., Som, D., Kanungo, S., Sahatiya, P*. Investigation of the Transduction Mechanism of Few Layer SnS2  for Pressure and Strain Sensing. Experimental Correlation with First Principle Study. IEEE Sensors Journal, 2021 (Accepted Manuscript)

56. Adepu, V, Kamath, K., Mattela, V., Sahatiya, P*. Laser Assisted Gaussian Microstructure Patterned PDMS Encapsulated Ti3C2Tx (MXene) based pressure sensor for Object and Touch Detection. IEEE Sensors Journal, 2021 (Accepted Manuscript).  

55. Adepu, V., Mattela, V., Sahatiya, P.* Remarkably Ultra-sensitive Large Area Matrix of MXene based Multifunctional Physical Sensors (Pressure, Strain and Temperature) for mimicking human skin. Journal of Materials Chemistry B, 2021. (Accepted Manuscript).  

54. Enaganti, P., Selamneni, V., Sahatiya, P*., Goel S*. MoS2/cellulose paper coupled with SnS2 Quantum Dots as 2D/0D electrode as high performance flexible supercapacitor. New Journal of Chemistry, 2021 (Accepted Manuscript)  

53. Battina, S., Kothuru, A., Sahatiya, P., Goel, S., Nandi, S. Laser Induced Graphene Printed Wearable Flexible Antenna Based Strain Sensor for Wireless Human Motion Monitoring. IEEE Transactions on Electronic Devices. 2021 (Accepted Manuscript).  

52. Adepu, V., Bokka, N., Mattela, V., Sahatiya, P*., Highly Electropositive ReS2 based Ultra-sensitive Flexible Humidity Sensor for Multifunctional applications. New Journal of Chemistry, 2021 (Accepted Manuscript) 

51. Bokka, N., K G Sankalp., Sahatiya P* Large area deposition of MoS2xSe2(x-1) on paper as electromechanical sensor for versatile physiological signal monitoring. Flexible and Printed Electronics, 2021 (Accepted Manuscript)

50. Selamneni, V., Kanungo, S., Sahatiya, P* Large area growth of SnS2/Graphene on Cellulose paper as a flexible broadband Photodetector and investigating the band structure through First Principle Simulations. RSC Materials Advances, 2021 (Accepted Manuscript) 

49. Bokka, N., Adepu V., Selamneni, V., Sahatiya, P* Non-contact, Controlled and Moisture Triggered Black Phosphorous Quantum Dots/PVA film for Transient Electronics Applications. Materials Letters, 2021 (Accepted Manuscript)

48. Veeralingam, S., Sahatiya, P., Badhulika, S. Papertronics: Hand written MoS2 on paper based highly sensitive and recoverable pressure and strain sensor. IEEE Sensors Journals, 2021 (Accepted Manuscript) 

47.  Selamneni, V., Harini R., Haza, A., Sahatiya, P*., MoS2 paper decorated with metal nanoparticles (Au, Pt and Pd) based plasmonic enhanced broadband (Vis-NIR) flexible photodetector. Advanced Materials Interfaces, 2021 (Accepted Manuscript)

46. Selamneni V., K G Sankalp., Nerurkar N., Akshaya T., Sahatiya, P*.,  Facile Fabrication of MoSe2 on Paper as an Electromechanical Piezoresistive Pressure Strain Sensor. IEEE Transactions on Instrumentation and Measurements, 2020 (Accepted Manuscript). 

45.  Selamneni. V., Dave, A., Mihailovic, P., Mondal, S., Sahatiya, P*. Large Area Pressure Sensor for Smart Floor Applications - An Occupancy Limiting Technology to Combat Social Distancing. IEEE Consumer Electronics Magazine, 2020 (Accepted Manuscript). 

44.  Selamneni. V., Kunchur, A., Sahatiya P*. Large Area, Flexible SnS/Paper based Piezoresisitive Pressure Sensor for Artificial Electronic Skin Application. IEEE Sensors Journal, 2020 (Accepted Manuscript)

43. Leelasree., Selamneni. V., Akshaya T., Sahatiya, P., Aggarwal., H. MOF Based Flexible, Low-Cost Chemiresistive Device as a Respiration Sensor for Sleep Apnea Diagnostics. Journal of Materials Chemistry B, 2020 (Accepted Manuscript)  

42.  Bokka, N., Selamneni, V, Sahatiya, P*. Water Destructible SnS2 QD/PVA Film Based Transient Multifunctional Sensor and Machine Learning Assisted Stimulus Identification for Non-Invasive Personal Care Diagnostics. Materials Advances, 2020 (Accepted Manuscript) 

41.  Selamneni, V., Gohel, K., Bokka, N., Sharma S., Sahatiya, P*., MoS2 based Multifunctional Sensor for Both Chemical And Physical Stimuli and their Classification Using Machine Learning Algorithm. IEEE Sensors Journal, 2020 (Accepted Manuscript)

40. Bharadwaj, R., Selamneni, V., Thakur, U., Sahatiya, P*., Hazra, A*., Detection and Discrimination of Volatile Organic Compounds by Nobel Nanoparticles Functionalized MoS2 coated biodegradable paper sensors. New Journal of Chemistry, 2020 (Accepted Manuscript)

39.  Selamneni. V,  K G Sankalp  Sahatiya, P*. All MoS2 based 2D/0D Localized Unipolar Heterojunctions as a Flexible Broadband (UV-Vis-NIR) Photodetector. Journal of Materials Chemistry C, 2020 (Accepted Manuscript)

38.   K G Sankalp, Selamneni. V,  Sahatiya, P*. Water Dissolvable MoS2 Quantum Dots/PVA film as an Active Material for Destructible Memristor. New Journal of Chemistry, 2020 (Accepted Manuscript) (Selected as Cover Article)

37.  Selamneni., V, B S Amogh., Sahatiya, P*. Highly Air Stabilized Black Phosphorous on disposable paper substrate as a tunneling effect based highly sensitive piezoresistive strain sensor. Medical Devices and Sensors, 2020 (Accepted Manuscript)

36. Selamneni., V, Nerurkar, N., Sahatiya, P* Large Area Deposition of MoSe2 on paper as a Flexible Infrared Photodetector, IEEE Sensors Letters, 2020 (Accepted Manuscript).  

35. Chandrasekhar Reddy K,  Sahatiya, P. Santos-Saucedaa, O. Cortazara, R. Ramírez Bon a . One Step Fabrication of 1D p-NiO nanowire/Si heterojunction: Development of Self powered Ultraviolet Photodetector, Applied Surface Science, 2020 (Accpeted Manuscript)  

34.  Selamneni., V, Sahatiya, P*.Bolometric effect enhanced Ultrafast Graphene based Do-it-yourself (DIY) wearable respiration sensor for personal healthcare monitoring, IEEE Sensors Journal, 2019 (Accepted Manuscript)

33.  Selamneni., V, Barya., P., Deshpande, N., Sahatiya, P*.  Low-cost, disposable, flexible and smartphone enabled pressure sensor for monitoring drug dosage in smart medicine applications. IEEE Sensors Journal, 2019 (Accepted Manuscript).

32. Joshna, P., Rao, S. G., Raj, P. M. P., Rao, B. P., Sahatiya, P., & Kundu, S. Plasmonic Ag nanoparticles arbitrated enhanced photodetection in p-NiO/n-rGO heterojunction for future self-powered UV photodetectors. Nanotechnology, 2019, (Accepted Manuscript) 

CONFERENCES 

1. Sankalp K G, Venkatarao Selamneni and Parikshit Sahatiya, International Conference on Nanoscience and Technology, (ICONSAT), Kolkata, Mar' 2020. 

2. Venkatarao Selamneni, Sankalp  K G, Nikita Nerurkar and Parikshit Sahatiya,  International Conference on Nanoscience and Technology, (ICONSAT), Kolkata, Mar' 2020

3. Amogh B.S, Venkatarao Selameni and Parikshit Sahatiya, International Conference on Nanoscience and Technology, (ICONSAT), Kolkata, Mar' 2020 

4. Venkataro Selamneni and Parikshit Sahatiya, International Workshop on Physics of Semiconductor Devices, (IWPSD), Kolkata, Dec' 2019.  

5. Venkatarao Selamneni and Parikshit Sahatiya, IEEE NMDC, Stockholm, Sweden, Oct' 2019.

6. Parikshit Sahatiya. Symposium on Carbon Nanomaterials Electronics (SCNE),  2019, BITS Pilani, Pilani Campus (Invited Talk)

 WITH IITH AFFILIATION (PhD and Post PhD work)

31. Veeralingam S., Sahatiya, P., Badhulika, S. First demonstration of low cost, flexible and disposable SnSe2 based photoresponsive ammonia sensor for detection of Ammonia in urine samples. Sensors and Actuators B: Chemical, 2019, (Accepted Manuscript)  

·  S30. Sahatiya, P., Jones, S. S., Mattela, V., & Badhulika, S. Direct growth of Black phosphorous (p type) on flexible substrate with dual role of 2D ZnO (n type) as effective passivation and enabling highly stable broadband photodetection. ACS Applied Electronic Materials, 2019 (Accepted Manuscript). 

29. Yalagala, B., Sahatiya, P., Mattela, V., & Badhulika, S. Ultra low-cost, large area Graphene-MoS2 piezotronic memristor on paper. A systematic study to both DC and AC inputs. ACS Applied Electronic Materials, 2019. (Accepted Manuscript) (Equal contributed First author)

 28. Vishnu, N. Sahatiya, P. Chang, K. Badhulika, S. Large area, one step synthesis of NiSe2 films on cellulose paper for glucose monitoring in bio-mimicking samples for clinical diagnostics. Nanotechnology, 2019 (Accepted Manuscript) (Equal contributed First Author)

27. C. Madhava., Sahatiya, P., Badhulika, S., Monitoring of physiological body signals and human activity based on ultra-sensitive tactile sensor by direct growth of ZnSnO3 nanocubes on silica cloth. Materials Science in Semiconductor Processing, 2019 (Accepted Manuscript) (Equal Contributed First Author) 

26. 26. Veeralingam S., Sahatiya, P., Kadu, A., Mattela, V., & Badhulika, S. Direct one step growth of NiSe2 on cellulose paper: A low cost, flexible, wearable with smartphone enabled multifunctional sensing platform for customized non-invasive personal healthcare monitoring. ACS Applied Electronic Materials, 2019. (Accepted Manuscript) (Equal Contributed First author) 

25. Yalagala, B., Sahatiya, P., Kolli, C. S. R., Khandelwal, S., Mattela, V., & Badhulika, S. V2O5 Nanosheets for Flexible Memristors and Broadband Photodetectors. ACS Applied Nano Materials, 2019. (Accepted Manuscript) (Equal contributed First author)

24. Sahatiya, P., Shinde, A., Kadu, A., & Badhulika, S. Functionalized water soluble nanomaterials and their applications in wirelessly destructible programmed flexible transient photodetectors. Materials Science in Semiconductor Processing, 2019, 93, 324-330. 

23. Sahatiya, P., Anand Kadu, Harshit Gupta, P Thanga Gomathi & Badhulika S, Flexible, disposable, cellulose paper based MoS2-Cu2S hybrid for wireless environmental monitoring and multifunctional sensing of chemical stimuli. ACS Applied Materials & Interfaces, 2018, 10(10), 9048-9059. Impact factor: 8.097  

22. P. Thanga Gomathi, Sahatiya, P., & Badhulika S. Large-area, broadband photodetector based on ZnS-MoS2 hybrid on paper substrate. Advanced Functional Materials, 2017, 27, 31. 1703611. (Equal contributed first author). Impact factor: 13.325 

21. Sahatiya, P., & Badhulika S. Wireless, smart, human motion monitoring using solution processed fabrication of Graphene-MoS2 transistor on paper. Advanced Electronic Materials, 2018, 1700388. Impact factor: 5.466 

20. Sahatiya, P., Jones, S. S., Gomathi, P. T., & Badhulika, S. Flexible substrate based 2D ZnO (n)/graphene (p) rectifying junction as enhanced broadband photodetector using strain modulation. 2D Materials, 2017, 4(2), 025053. Impact factor: 7.042 

19.  Sahatiya, P., & Badhulika S. Fabrication of solution processed, highly flexible few layer MoS2 (n) – CuO (p) piezotronic diode on paper substrate for active analog frequency modulator and enhanced broadband photodetector. Journal of Material Chemistry C, 2017, 5(44), 11436-11447. Impact factor: 5.976

18. Sahatiya, P., Chandrasekhar Reddy K., & Badhulika S. Discrete distribution of 1D V2O5 nanowires over 2D MoS2 nanoflakes for enhanced broadband flexible photodetector covering Ultraviolet to Near Infrared region. Journal of Material Chemistry C, 2017, 5, 12728-12736. Impact factor: 5.976

17. Sahatiya, P., Kannan, S., & Badhulika, S. Few layer MoS2 and in situ poled PVDF nanofibers on low cost paper substrate as high performance piezo-triboelectric hybrid nanogenerator: Energy harvesting from handwriting and human touch. Applied Materials Today, 2018, 13, 91-99. Cite Score: 9.90 (Impact factor – NA)

16.  Sahatiya, P, S. Solomon Jones., & Badhulika S. 2D MoS2-carbon quantum dot hybrid based large area, flexible UV-vis-NIR photodetector on paper substrate. Applied Materials Today, 2018, 10, 106-114. Cite Score: 9.90 (Impact factor – NA)

15. Sahatiya, P., & Badhulika, S. Eraser-based eco-friendly fabrication of a skin-like large-area matrix of flexible carbon nanotube strain and pressure sensors. Nanotechnology, 2017, 28(9), 095501. (Featured article). Impact factor: 3.404 

14. Sahatiya, P., Shinde, A., & Badhulika S. Pyro-phototronic nanogenerator based on flexible 2D ZnO/Graphene heterojunction and its application in self-powered Near Infrared photodetectors and active analog frequency modulation. Nanotechnology, 2018 (Accepted manuscript). Impact factor: 3.404 

13. Sahatiya, P., & Badhulika S., Strain modulation assisted enhanced broadband photodetector based on large area, flexible, few layered Graphene-MoS2 on cellulose paper. Nanotechnology, 2017, 28 (45), 455204. Impact factor: 3.404 

12. Sahatiya, P, S. Solomon Jones., & Badhulika S. Direct, large area growth of few layered MoS2 nanostructures on different flexible substrates: growth kinetics and its effect on photodetection studies. Flexible and Printed Electronics, 2018, 3(1), 015002. Impact factor: NA 

11. Sahatiya, P., Puttapati, S. K., Srikanth, V. V., & Badhulika, S. Graphene-based wearable temperature sensor and infrared photodetector on a flexible polyimide substrate. Flexible and Printed Electronics, 2016, 1(2), 025006. (Featured article). Impact factor: NA

10. Sahatiya, P, Chepuri Madhava, Shinde Akash & Badhulika S, Flexible substrate based few layer MoS2 electrode for passive electronic devices and interactive frequency modulation based on human motion. IEEE Transactions on Nanotechnology, 2017. (Accepted Manuscript). (Equal contributed first authors). Impact factor: 2.857 

9. Veerla Raja Sekhar, Sahatiya, P., & Badhulika S. Direct writing of ZnO pencil on paper based flexible UV photodetector and disposable photoresponsive Uric Acid sensor. Journal of Material Chemistry C, 2017, 5, 10231-10240. Impact factor: 5.976 

8. A. Gopalakrishnan, Sahatiya, P., & Badhulika. S. Template assisted electrospinning of bubbled carbon nanofibers (BCNFs) as binder-free electrode for high performance supercapacitors. ChemElectroChem, 2018, 5(3), 531-539. Impact factor: 4.446 

7.  S. Solomon Jones, Sahatiya, P., & Badhulika S. One step, high yield synthesis of amphiphilic carbon quantum dots derived from Chia seeds: A solvatochromic study. New Journal of Chemistry, 2017, 41(21), 13130-13139. Impact factor: 3.2 

6.  Kawahara, R., Sahatiya, P., Badhulika, S., & Uno, S. Paper based potentiometric pH sensor using carbon electrode drawn by pencil. Japanese Journal of Applied Physics, 2018, 57(4S), 04FM08. Impact factor: 2.176 

5. A. Gopalakrishnan., Sahatiya, P., & Badhulika. S. Low temperature, one-pot green synthesis of tailored carbon nanostructures/reduced graphene oxide composites and its investigation in supercapacitor applications. Materials letters, 2017, 198, 46-49. Impact factor:  2.687 

4.  Sahatiya, P., Gomathi, P. T., Jones, S. S., & Badhulika, S. Sponge and graphene/PVDF/ZnO composite based 3D stacked flexible multi-sensor platform. MRS Advances, 2016, 1-7. Impact factor: NA 

3. Sahatiya, P., & Badhulika, S. Solvent-free fabrication of Multi-walled carbon nanotube based flexible pressure sensor for ultra-sensitive touch pad and electronic skin applications. RSC Advances, 2016. Impact factor: 2.936 

2. Sahatiya, P., & Badhulika, S. UV/ozone assisted local graphene (p)/ZnO (n) heterojunctions as a nanodiode rectifier. Journal of Physics D: Applied Physics, 2016, 49(26), 265101. Impact factor: 2.373 

1.  Sahatiya, P., & Badhulika, S. One-step in situ synthesis of single aligned graphene–ZnO nanofiber for UV sensing. RSC Advances, 2015, 5(100), 82481-82487. Impact factor: 2.936 

Conferences (International and National) 

1. Sahatiya, P & Badhulika, S. One step growth of few layer MoS2 on pencil for different flexible electronic components and broadband photodetector on paper substrate. MRS 2018 Spring Meet, Phoenix, Arizona, USA (Poster presentation)

2. P. Thanga Gomathi, Sahatiya, P, Pittsburgh, USA. (Oral presentation). and Sushmee Badhulika. Solution processed ZnS-MoS2 for optoelectronic applications. IEEE Nano 2017

3. Sahatiya, P. Arthi Gopalakrishnan and Sushmee Badhulika. Large area Graphene-MoS2 visible light photodetector. IEEE Nano 2017, Pittsburgh, USA. (Oral presentation)

4. Sahatiya, P, Solomon Jones, P. Thanga Gomathi and Sushmee Badhulika. Flexible substrate based 2D graphene (p)/ ZnO (n) heterojunction architecture as nanodiode rectifier. ICEE conference, IIT Bombay, Dec 2016. (Oral presentation)

5. Arthi, G; Sahatiya, P.; & Badhulika, S. Electrospun mesporous silica templated hybrid carbon nanofibers for supercapacitor electrodes. International Conference of Young Researchers on Advanced Materials, IISC Bangalore, India, 2016 (Best Poster Award)

6. Sahatiya, P, Arijit Sen., “Stroboscopic Wave packet Description for transient current in nanodevices,” International Conference On Nanoscience and Technology (ICONSAT). Chandigarh, Punjab, India, 2014. (Poster presentation)

7. Kumar, Niraj, Sahatiya, P.; & Pranay Dubey. "Fabrication of CNT based Gas Sensor Using Interdigitated Gold Electrodes." Procedia Materials Science 6, 2014, 1976-1980. (Oral presentation)

Book Chapters 

1. Sahatiya, P., & Badhulika, S. Graphene Hybrid Architectures for Chemical Sensors. In Graphene-based Materials in Health and Environment. Springer International Publishing, 2016, 259-285

2.  Sahatiya, P., Sha, R., & Badhulika, S. Flexible 2D electronics in sensors and bioanalytical applications. Handbook on Flexible Electronics. CRC press (in press)

Dr. Amit Kumar Panda

1. R. Palisetty, A. K. Panda and K. C. Ray, “ASIC Implementation of Low PAPR Multidevice Variable-Rate Architecture for IEEE 802.11ah,” in IEEE Transactions on Instrumentation and Measurement, vol. 70, pp. 1-10, 2021, Art no. 2002810, doi: 10.1109/TIM.2020.3045809. (Impact Factor: 3.658) Link

2. A. K. Panda, R. Palisetty and K. C. Ray, “High-Speed Area-Efficient VLSI Architecture of Three-Operand Binary Adder,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 11, pp. 3944-3953, Nov. 2020, doi: 10.1109/TCSI.2020. (Impact Factor: 3.318) Link

3. A. K. Panda and K. C. Ray, “A Coupled Variable Input LCG Method and its VLSI Architecture for Pseudorandom Bit Generation,” in IEEE Transactions on Instrumentation and Measurement, vol. 69, no. 4, pp. 1011-1019, April 2020, doi: 10.1109/TIM.2019.2909248. (Impact Factor: 3.658) Link

4. A. K. Panda and K. C. Ray, “Modified Dual-CLCG Method and its VLSI Architecture for Pseudorandom Bit Generation,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 3, pp. 989-1002, March 2019, doi: 10.1109/TCSI.2018.2876787. (Impact Factor: 3.318) Link