Frequency Dividers & Multipliers

Introduction

Digital systems often require clocks of different frequencies for different modules. A frequency divider reduces the input clock frequency by a fixed factor, while a frequency multiplier increases it. These circuits are widely used in SoCs for tasks like generating baud rates, creating low-power clock domains, or deriving high-speed clocks from a base reference.

While frequency dividers can be implemented using simple counters and flip-flops in digital logic, frequency multipliers are typically realized using techniques like phase-locked loops (PLLs) or by exploiting both edges of a clock. Together, these blocks form the foundation of clock generation and management in modern designs.

Problem

In complex digital systems, not all modules can operate on the same clock frequency.

High-speed modules (like processors or serial links) often require faster clocks.
Peripheral or low-power modules may run at much slower rates to save power.
Certain applications (e.g., UART, I²C) need clocks derived at specific ratios of a system clock.

If only a single base clock is distributed, it cannot meet the needs of all blocks. Simply gating or stretching clocks can also lead to glitches and timing violations. Hence, dedicated frequency dividers and multipliers are used to generate clean, phase-consistent clocks at the required rates.

Frequency Divider

Frequency Divider For f/n, where n is a Natural Number (f/2, f/3, f/4, etc.) using MOD-N Counter

Mod-N counter: Count 0→N−1 on the input clock and tap any state bit to get an output at f/N (or use a 1-cycle pulse every N counts as a clock-enable).
Phase adjustment with flip-flops:
1. Positive-edge DFF after the tap shifts the signal by +1 input-clock cycle.
2. Negative-edge DFF after the tap shifts the signal by +½ input-clock cycle.
Pick the output of Mod-N with minimal post-conditioning: Choose the counter output whose phase/duty is closest to what you need so you require the least extra hardware (e.g., fewer flops/gates for phase align or duty correction).

Example 1: Frequency divider by 3

Step 1: Start by implementing a Mod-3 counter driven by the input clock. The counter cycles from 0 to 2 and then resets, producing periodic outputs.

Each counter bit naturally divides the input frequency by a power of 2, while a complete cycle of the counter corresponds to a frequency of f/3. These outputs form the basis from which the desired divided clock will be selected.

Step 2: The Q1 output stays high for 1 clock cycle and low for 2 clock cycles, giving it a duty cycle of ~33%. To correct this toward 50%, we introduce a half-clock-cycle phase shift to Q1. This is achieved by passing Q1 through a negative-edge triggered D flip-flop, producing Q2, which is effectively Q1 delayed by half a clock cycle.

Step 3: Finally, combine Q1 and its half-cycle–shifted version Q2 (from the negative-edge DFF). By OR-ing these two signals, the resulting output stays high for 1.5 clock cycles and low for 1.5 clock cycles, yielding a clean 50% duty cycle clock at f/3.

Example 2: Frequency divider by 5 (Try yourself first)

Step 1: Start by implementing a Mod-5 counter driven by the input clock. The counter cycles from 0 to 4 and then resets, producing periodic outputs.

Each counter bit naturally divides the input frequency by a power of 2, while a complete cycle of the counter corresponds to a frequency of f/5. These outputs form the basis from which the desired divided clock will be selected.

Draw the waveforms for this example yourself

Step 2: The Q1 output stays high for 2 clock cycle and low for 3 clock cycles, giving it a duty cycle of 40%. To correct this toward 50%, we introduce a half-clock-cycle phase shift to Q1. This is achieved by passing Q1 through a negative-edge triggered D flip-flop.

Step 3: Finally, combine Q1 and its half-cycle–shifted version (from the negative-edge DFF). By OR-ing these two signals, the resulting output stays high for 2.5 clock cycles and low for 2.5 clock cycles, yielding a clean 50% duty cycle clock at f/5.

Example 3: Frequency divider by 6

Step 1: Start by implementing a Mod-6 counter driven by the input clock. The counter cycles from 0 to 5 and then resets, producing periodic outputs.

Each counter bit naturally divides the input frequency by a power of 2, while a complete cycle of the counter corresponds to a frequency of f/6. These outputs form the basis from which the desired divided clock will be selected.

Step 2: The Q2 output stays high for 2 clock cycle and low for 4 clock cycles, giving it a duty cycle of 33.33%. To correct this toward 50%, we introduce a one-clock-cycle phase shift to Q2. This is achieved by passing Q2 through a positive-edge triggered D flip-flop.

Step 3: Finally, combine Q2 and its one-cycle–shifted version (from the positive-edge DFF). By OR-ing these two signals, the resulting output stays high for 3 clock cycles and low for 3 clock cycles, yielding a clean 50% duty cycle clock at f/6.

2. Frequency Divider For f/n, where n is a Fraction Number (f/1.5, f/2.5, f/3.5, etc.) using MOD-N Counter

Four building blocks are used to implement a Frequency divider by a fractional number: Clock Frequency Divider by an integer, a delay module, XOR Gate, XNOR Gate.
Multiply n by 2 and get frequency (f/2n) to be generated by an integer clock frequency divider. It's easy to generate f/2n as 2n is an integer number.
Depending upon the duty cycle, decide the number of flip-flops to be added in the delay module. Each delay module increases the duty cycle by 1/2n.

Example 1: Frequency divider by 1.5

Step 1: Start by implementing a F/3 frequency divider driven by the input clock.

Step 2: Add delay blocks depending upon the duty cycle. Each delay module increases the duty cycle by 1/3.

Step 3: Use an XOR gate to get the desired output.

Example 2: Frequency divider by 2.5

Step 1: Start by implementing a F/5 frequency divider driven by the input clock.

Step 2: Add delay blocks depending upon the duty cycle. Each delay module increases the duty cycle by 1/5.

Step 3: Use an XOR gate to get the desired output.

3. Frequency divider using Ring Counter

Include an N-bit ring Counter. The output of each FF inside the ring counter is a signal of frequency f/n and duty cycle 1/n.
OR operation on consecutive ring counter FF adds 1/n to it's duty cycle, while negative edge FF adds 0.5/n to it's duty cycle.

Example : Frequency divider by 5

Step 1: Include a 5-bit ring counter.

Step 2: Output of all FFs is a signal of frequency f/5 and duty cycle 1/5 (20%).

Note: FFn refers to neg-edge Flip-Flop

Frequency Multiplier

Step 1: Draw the input clock (f_in) waveform and the desired output clock (f_out = 2 × f_in).

Step 2: XORing f_in with n delayed inputs results in signal with frequency f/n; the amount of delay determines the exact phase of each waveform.

Step 3: Combine f_in and all its delayed versions using an XOR operation. The result is a reconstructed waveform that toggles twice for every cycle of f_in, effectively generating f_out = 2 × f_in.

Example 1: Frequency multiplier by 2

Step 1: Draw the input clock (f_in) waveform and the desired output clock (f_out = 2 × f_in).
Step 2: Pass f_in through a delay element. The delay is chosen such that the delayed edge lies exactly midway between two consecutive edges of f_in — i.e., both edges are equidistant.
Step 3: Perform an XOR operation between f_in and its delayed version. This ensures that a transition occurs at both the original clock edge and the delayed edge, giving a clean output at 2 × f_in with a 50% duty cycle.

This is a sample delay control circuit, based on select lines.

Depending on the select line, the amount of delay is decided; which decides the duty cycle.

Note: Since only one delayed input is given in XOR along with fin, the fout will always be 2f.

Example 2: Frequency multiplier by 3

Step 1: Draw the input clock (f_in) waveform and the desired output clock (f_out = 3 × f_in).
Step 2: Pass f_in through 2 delay element. The delay is chosen such that the delayed edges and original clock edge are equidistant.
Step 3: Perform an XOR operation between f_in and its delayed versions. This ensures that a transition occurs at both the original clock edge and the delayed edge, giving a clean output at 3 × f_in with a 50% duty cycle.

Example 3: Frequency multiplier by 5

Step 1: Draw the input clock (f_in) waveform and the desired output clock (f_out = 5 × f_in).
Step 2: Pass f_in through 4 delay element. The delay is chosen such that the delayed edges and original clock edge are equidistant.
Step 3: Perform an XOR operation between f_in and its delayed versions. This ensures that a transition occurs at both the original clock edge and the delayed edge, giving a clean output at 5 × f_in with a 50% duty cycle.

Fractional Frequency Multiplier

Create a higher multiple first, then divide.

General rule: f_out = f_in × (p/q) → multiply by p, then divide by q.(Both p & q are integers)
Example: To get 1.5×f, first generate 3×f, then pass it through a ÷2 divider → f_out = 3f/2 = 1.5f.

Note: In real hardware, the “×p” stage is typically done with a PLL/DLL (clean edges), and the divide stage with a counter.

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