Biography

Juei-Chin Shen received the PhD degree from the University of Manchester in 2013. He was with the Hong Kong University of Science and Technology (HKUST) from 2013 to 2015 as a Research Associate, and then with Mediatek Inc. as a Senior Engineer. Later, he joined Realtek Inc. as an Assistant Project Manager in 2019, working on 10G Ethernet PHY and digitally assisted analog circuit design. Since 2022, he has been with National Taipei University as an Assistant Professor. His career interest is R&D on next generation communications systems, including advanced technology exploration and IPR development, as well as system design, verification and prototyping. Shen has produced seven journal articles and seven conference papers, which have already been published in leading IEEE journals or fl agship conferences. He is co-recipient of IEEE PIMRC’2014 Best Paper Award and co-author of 2018 IEEE Signal Processing Society Young Author Best Paper.

Honors and Awards

2018 Co-author of IEEE Signal Processing Society Young Author Best Paper

2014 IEEE PIMRC’2014 Best Paper Award

Work Experience

2022 Feb. ~ Now, Assistant Professor, National Taipei University, Taiwan.

Teaching: Information Theory, Signal Integrity, Data Structures, Design and Implementation of Wireline Communication.

2019 Mar. ~ 2022 Jan., Assistant Project Manager, Realtek, Taiwan.

10G Ethernet Algorithm Design:

DAC calibration for echo reduction: Propose using digital-domain current switch sequence re-arrangement for multiple-DAC mismatch calibration.
Analog front-end (AFE) modeling: DAC random current mismatch, transmitter-side jitter effects, transform s-parameter to channel impulse response, analog circuit channel & noise estimation.
Color filter design for RFI interference reduction: Propose a stochasitc approach to optimizing filter design.
Theorectical performance analysis of MIMO MMSE-DFE system under practical feedforward & feedback equalizer constraints.

2015 Jun. ~ 2019 Feb., Senior Engineer, Mediatek, Taiwan.

5G Sub-6G Prototyping:

Algorithm design of timing & frequency offset tracking by using deomodulation reference signal.
Fixed-point block diagram for hardware implementation.
Verification & debugging on target platform.

5G Sub-6G Modem:

Algorithm design of channel average delay & delay spread estimation: Propose new 2D hypothesis testing metric leading to more reliable estimate over wider SNR region.
Block diagram for firmware implementation.

5G Above-6G Modem:

Algorithm design (mutual information based) of mmWave antenna subarray down-selection.
Control path design of mmWave beam management, including initial & steady state operation.
Evaluate the impact of different mmWave antenna in package (AiP) designs on link-level performance.

2013 Dec. ~ 2015 May, Research Associate, Hong Kong University of Science & Technology, Hong Kong.

Analyzing the downlink user capacity of massive MIMO systems under pilot contamination.
Developing a compressed-sensing-based approach to effi cient CSI acquisition in Massive MIMO.
Assisting with the preparation of a funding proposal:
1. General Research Fund (GRF) 2015/16, Hong Kong.
2. NSFC/RGC Joint Research Scheme 2015/16, Hong Kong.