Pubulications

2026

J. Yun and J. Rhee "A Fully Integrated 16-MHz Voltage-Mode Relaxation Oscillator with Current Calibration for Temperature Compensation," in  IEEE Transactions on Circuits and Systems II: Express Briefs(ealry access), 2026

S. Seo, J. Lee, J. Kim, Y. Chang, J. Yun, Y.-U. Jeong, and W.-S. Choi, “A Single-Ended MTA PAM-4 Receiver With Analog-Front-End Nonlinearity Compensation Using MTA-Error Correction Scheme for Memory Interfaces,” IEEE Access, vol. 14, pp. 6219–6228, 2026.

2025

J. Kim, S. Seo, J. Lee, J. Yun, and S. Kim, “A 24-Gb/s/pin Single-Ended PAM-3 Transmitter With 8-bit/6-UI Encoding based partial-MTA for Low-Power Memory Interfaces,” in 2025 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 1–3, 2025.

J. Kim, S. Lee, J. Yun, S. Seo, K. Lee, Y.-U. Jeong, and S. Kim, “Energy-Efficient Single-Ended Capacitive PAM-4 Transceiver for Next-Generation HBM Interfaces,” in 2025 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 1–6, 2025.

J. Lee, Y. Chang, J. Yun, S. Seo, Y.-U. Jeong, and S. Kim, “MTA-Coded PAM-4 Receiver with Decision Feedback Power Saving Scheme and Partial DFE for Low-Power Memory Interfaces,” in 2025 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 1–6, 2025.

2024

J. Yun, S. Lee, J. Kim, J.-H. Chae, S. Kim, and Y.-U. Jeong, “A Single-Ended Impedance-Matched Transmitter With Single Ring-Oscillator-Based Time-Domain ZQ Calibration for Memory Interfaces,” IEEE Journal of Solid-State Circuits, vol. 59, no. 9, pp. 2971–2982, 2024.

S. Seo, Y.-U. Jeong, J. Yun, J. Kim, and S. Kim, “A 0.77-pJ/bit 40-Gb/s/pin Single-Ended Hybrid DAC-Based Transmitter for Memory Interfaces,” in 2024 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5, 2024.

2023

J. Kim, J. Yun, J.-H. Chae, and S. Kim, “A 50–1600 MHz Wide-Range Digital Duty-Cycle Corrector With Counter-Based Half-Cycle Delay Line,” IEEE Access, vol. 11, pp. 30555–30561, 2023.

2022

Y.-U. Jeong, S. Choi, J.-H. Chae, J. Yun, S.-H. Jeong, and S. Kim, “A 10 Gb/s/pin Single-Ended Transmitter With Reflection-Aided Duobinary Modulation for Dual-Rank Mobile Memory Interfaces,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 3, pp. 1125–1134, 2022.

S. Lee, Y.-U. Jeong, J. Yun, J.-H. Chae, and S. Kim, “A Low-Power DRAM Transmitter With Phase and Current-Mode Amplitude Equalization to Improve Impedance Matching,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 11, pp. 4208–4212, 2022.

S. Lee, J. Yun, and S. Kim, “A 78.8fJ/b/mm 12.0Gb/s/Wire Capacitively Driven On-Chip Link Over 5.6mm with an FFE-Combined Ground-Forcing Biasing Technique for DRAM Global Bus Line in 65nm CMOS,” in IEEE International Solid-State Circuits Conference (ISSCC), pp. 454–456, 2022.

2020

Y.-U. Jeong, J. Park, M. Kim, J.-H. Chae, J. Yun, H. Lee, and S. Kim, “A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 9, pp. 1589–1593, 2020.

S. Lee, H.-G. Ko, J.-H. Chae, S. Shin, J. Yun, D.-K. Jeong, and S. Kim, “A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 10, pp. 1735–1739, 2020.

S. Shin, H.-G. Ko, C.-H. Kye, S.-Y. Lee, J. Yun, D. Lee, H.-K. Jung, S. Kim, and D.-K. Jeong, “A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 10, pp. 1814–1818, 2020.

J. Yun, S. Lee, Y.-U. Jeong, S.-H. Jeong, and S. Kim, “A 0.4–1.7GHz Wide Range Fractional-N PLL Using a Transition-Detection DAC for Jitter Reduction,” in 2020 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 1–4, 2020.

2019

Y.-U. Jeong, J.-H. Chae, S. Choi, J. Yun, S.-H. Jeong, and S. Kim, “A Low-Power and Low-Noise 20:1 Serializer with Two Calibration Loops in 55-nm CMOS,” in 2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 1–6, 2019.

H.-G. Ko, S. Shin, C.-H. Kye, S.-Y. Lee, J. Yun, H.-K. Jung, D. Lee, S. Kim, and D.-K. Jeong, “A 370-fJ/b, 0.0056 mm²/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop,” in 2019 Symposium on VLSI Circuits, pp. 94–95, 2019.

2018

J.-W. Lee, J.-H. Chae, J. Park, H. Park, J. Yun, and S. Kim, “Energy-Efficient Dynamic Comparator with Active Inductor for Receiver of Memory Interfaces,” in 2018 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), pp. 10:1–10:6, 2018.