• 1. (2024) Phase-Locked Loops: System Perspectives and Circuit Design Aspects. WILEY-IEEE PRESS.

  2. (2020) Phase-Locked Frequency Generation and Clocking: Architectures and Circuits for Modern Wireless and Wireline Systems, Edited, THE INSTITUTION OF ENGINEERING AND TECHNOLOGY (IET).

  3. (2015) Wireless Transceiver Circuits: System Perspectives and Design Aspects, Edited, CRC PRESS.

• 1. (2026) A Coherent Polar Phase-Tracking Receiver With High ACR and Relaxed I/Q Generation . IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC). Accepted (available in IEEE Early Access)

  2. (2026) A 1.8-Gb/s PSK-UWB CMOS Transceiver With Extended PPM/PWM Modulation and Costas-Loop Carrier Synchronization. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I (TCAS-I). Accepted (available in IEEE Early Access)

  3. (2026) A 0.015-mm^2 0.5-V Synthesizable Hybrid PLL With Multiphase Linear Proportional-Gain Paths. IEEE SOLID-STATE CIRCUITS LETTERS, 9.

  4. (2025) A 0.6-V Fully-Integrated BLE Transmitter in 65-nm CMOS Using a Common-Mode-Ripple-Cancelled Hybrid PLL and a Duty-Cycle-Controlled Class-E/F2 PA Achieving 25% System Efficiency at 0 dBm. IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC). 60, 10.

  5. (2025) A 27.9-mW 802.15.4/4z 1T2R Transceiver with FIR-Embedded Quadrature Hybrid Correlation and AoA Localization. IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC). 60, 9.

  6. (2025) A Polar Phase-Tracking Receiver With Two-Point Injection Technique. IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC). 60, 5.

  7. (2025) An Ultra-Low-Voltage Bias-Current-Free Fractional-N Hybrid PLL With Voltage-Mode Phase Detection and Interpolation. IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC). 60, 1.

  8. (2024) An IEEE 802.15.4/4z Coherent Quadrature Hybrid Correlation UWB Receiver in 65-nm CMOS. IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC). 59, 8.

  9. (2024) A Low-Complexity FM-UWB Transmitter with Digital Reuse and Analog Stacking. IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC). 59, 7.

  10. (2024) A 65-nm Sub-10-mW Communication/Ranging Quadrature Uncertain-IF IR-UWB Transceiver With Twin-OOK Modulation. IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC). 59, 6.

  11. (2024) A DTC-Free Fractional-N BBPLL With FIR-Embedded Injection-Locked-Oscillator-Based Phase-Domain Lowpass Filter. IEEE JOURNAL OF SOLID-STATE CIRCUITS (JSSC). 59, 3.

• 1. (2026) A 0.5V 13.7pJ/pulse 802.15.4/4z UWB Tag and Coherent Quadrature-Hybrid-Correlation Receiver Chipset for Passive Localization Systems. CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC).

  2. (2025) A Coherent Polar PT-RX for 32-APSK/16-QAM/GFSK Demodulation with High ACR and Relaxed I/Q Generation. ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC).

  3. (2025) Analysis and Design of Bias-Current-Free Hybrid PLLs with Multi-Phase Time-Interleaved Phase Detector. INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS).

  4. (2025) A 1.8Gb/s 8GHz PSK-UWB Transceiver with Extended PPM/PWM Modulation and Embedded Carrier Spreading. CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC).

  5. (2025) A 0.5V 0.55mm2 Bias-Current-Free BLE Transceiver with 1-Bit Delay-Based Demodulation for Energy-Harvesting IoT Applications. CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC).

  6. (2024) A 0.6V Fully-Integrated BLE Transmitter in 65nm CMOS Using a Common-Mode-Ripple-Cancelled Hybrid PLL and a Duty-Cycle-Controlled Class-E/F2 PA Achieving 25% System Efficiency at 0dBm. ASIAN SOLID-STATE CIRCUITS CONFERENCE (A-SSCC).

  7. (2024) A 2.3nJ/b 32-APSK Polar Phase-Tracking Receiver with Two-Point Injection Technique. RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM.

  8. (2024) A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS. INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE (ISSCC).

1. W. Rhee, X. Chen, J. J. Kim, D. W. Kim, Z. Wang, “Receiver, Method of Operating the Receiver, and Beamforming Radar System Including Receiver” US 9,791,561 B2, Oct. 17, 2017

2. W. Rhee, B. Zhou, J. J. Kim, D.-W. Kim, Z. Wang, “Transmitter and Receiver for Reducing Power Consumption in FM-UWB Communication System,” US 9,253,730 B2, Feb. 2, 2016

3. W. Rhee, F. Chen, J. J. Kim, D. W. Kim, Z. Wang, “Apparatus and Method for Ultra Wideband Communication Using Dual Band Pass Filter,” US 9,172,425 B2, Oct. 27, 2015

4. S. Geng, W. Rhee, J. J. Kim, D. W. Kim, Z. Wang, “Apparatus and Method for Generating Gaussian Pulse and Ultra Wideband Communication Apparatus for Generating Gaussian Pulse,” US 9,036,679 B2, May 19, 2015

5. W. Rhee, X. Yu, Y. Sun, S.-S. Ko, B.-H. Park, H.-K. Ahn, W.-S. Choo, Z. Wang, “Frequency Divider, Frequency Synthesizer and Application Circuit,” US 8,446,190 B2, May 21, 2013

6. W. Rhee, H. Rui, X. Yu, T.-Y. Oh, J.-S. Choi, Z. Wang, “Phase-Locked-Loop Circuit Including Digitally-Controlled Oscillator,” US 8,368,440 B2, Feb. 5, 2013

7. W. Rhee, X. Yu, S. C. Shin, Z. Wang, “Delay Locked Loop Using Hybrid FIR Filtering Technique and Semiconductor Memory Device Having the Same,” US 8,310,886 B2, Nov. 13, 2012

8. W. Rhee, X. Yu, J.-Y. Park, Z. Wang, “Delay Locked Loop and Method and Electronic Device Including the Same,” US 8,295,106 B2, Oct. 23, 2012

"In Step With Woogeun Rhee: Benefiting Humanity With Global Reach," IEEE Solid-State Circuits Magazine, vol. 14, Issue 1, pp. 97-99, Jan. 2022.