Using synchronous logic design and clocked cycles,
Counter counts based off a 50 Mhz clock cycle and to 999. At 999, it rolls voer and starts counting again from zero. The yellows line represent certain hex displays that are sent to the FPGA Board. Starting at the top of the yellow lines, the first one represents the ones place, the second line represents the tens place, and the last line represents the hundreds place. This counter can also be preset to an indicated number by the binary inputs switches.
Video representation:
Ice Cold Soda sold here! A functional vending machine was created and it had inputs of quarters, nickels, and dimes. Two of the outputers were LEDS that displayed if the user received change back or if the red bull was dispensed. There are two more outputs that are hex displays, they display the total amount of money inserted into the machine. To control the different outputs, inputs, situations and criteria for each event to happen, a state flow diagram was created. The State flow diagram shows which conditions lead to which states.
Figure 1: State Flow Diagram for the vending machine.
Figure 2: This simulation waveform shows the state machine starting in the wait1 state and then the inputs of quarter, nickel, and dime changing the money value. Hex1 represents the tens digit of cents and hex0 represents the single digits of cents.
Figure 3: This simulation waveform shows that the user inserted an extra quarter, making the total money in the vending machine at 90 cents. The current state becomes vending and the new total money becomes 15.
The final design was capable of performing multiplication, division, subtraction, and addition with integers and displaying the correct value. The calculator made in this assignment can also be expanded on easily because of the use of components. To add another hex display, you only have to add another Port Map of that component and assign the new additional pins. The math of the top level entity can be easily changed since it was outside of the components and in the architecture of the top level entity.