Publication

Journal articles & book chapters:

B. -C. Wu, W. -T. Chen and T. -T. Liu, "An Error-Resilient RISC-V Microprocessor With a Fully Integrated DC–DC Voltage Regulator for Near-Threshold Operation in 28-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 58, no. 11, pp. 3275-3285, Nov. 2023.
H. -C. Chang, T. Wang, C. -A. Liao and T. -T. Liu, "A Low-Power PPG Processor for Real-Time Biometric Identification and Heart Rate Estimation," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 10, pp. 3932-3936, Oct. 2023.
C. -Y. Yao, T. -Y. Wu, H. -C. Liang, Y. -K. Chen and T. -T. Liu, "A Fully Bit-Flexible Computation in Memory Macro Using Multi-Functional Computing Bit Cell and Embedded Input Sparsity Sensing," in IEEE Journal of Solid-State Circuits, vol. 58, no. 5, pp. 1487-1495, May 2023.
R. -X. Zheng, Y. -C. Ko and T. -T. Liu, "A Speculative Computation Approach for Energy-Efficient Deep-Neural-Network," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 3, pp. 795-806, March 2023.
S. -H. Yang and T. -T. Liu, "A Highly Stable Physically Unclonable Function Using Algorithm-Based Mismatch Hardening Technique in 28-nm CMOS," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 1, pp. 280-289, Jan. 2023.
S. -H. Cheng, M. -H. Lee, B. -C. Wu and T. -T. Liu, "A Lightweight Power Side-Channel Attack Protection Technique with Minimized Overheads Using On-Demand Current Equalizer," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 10, pp. 4008-4012, Oct. 2022.
Y. -L. Liou, J. -Y. Hsu, C. -S. Chen, A. H. Liu, H. -Y. Lee and T. -T. Liu, "A Fully Integrated 1.7mW Attention-Based Automatic Speech Recognition Processor," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 10, pp. 4178-4182, Oct. 2022.
M. -G. Lin et al., "D-NAT: Data-Driven Non-Ideality Aware Training Framework for Fabricated Computing-In-Memory Macros," in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 12, no. 2, pp. 381-392, June 2022.
J. -J. Chou, T. -W. Chang, X. -Y. Liu, T. -Y. Wu, Y. -K. Chen, Y. -T. Hsu, C. -W. Chen, T. -T. Liu, and C. -S. Shih, "CIM-Based Smart Pose Detection Sensors," in Sensors, vol.22, no.9, pp.3491, 2022.
Y. -C. Lai, C. -Y. Yao, S. -H. Yang, Y. -W. Wu and T. -T. Liu, "A Robust Area-Efficient Physically Unclonable Function with High Machine Learning Attack Resilience in 28-nm CMOS," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 1, pp. 347-355, Jan. 2022.
T. ‐C. Chen, C. ‐C. Pai, Y. ‐Z. Hsieh, H. ‐Y. Tseng, James C.‐M., T. ‐T. Liu, and I. ‐W. Chiu, "Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits," Journal of Electronic Testing, 37, pp. 453–471, 2021.
Y. -T. Hsu, C. -Y. Yao, T. -Y. Wu, T. -D. Chiueh and T. -T. Liu, "A High-Throughput Energy-Area-Efficient Computing-in-Memory SRAM using Unified Charge-Processing Network," in IEEE Solid-State Circuits Letters, vol. 4, pp. 146-149, 2021.
P. -H. Chou, Y. -H. Yao, R. -X. Zheng, Y. -L. Liou, T. -T. Liu, H. -Y. Lane, A. -C. Yang, and S. -C. Wang, "Deep Neural Network to Differentiate Brain Activity Between Patients With First-Episode Schizophrenia and Healthy Individuals: A Multi-Channel Near Infrared Spectroscopy Study, " Front Psychiatry, 2021 Apr 15;12:655292.
C. -H. Lu, Y. -T. Hsu, B. -C. Wu and T. -T. Liu, "A 270-mV 6T SRAM Using Row-Based Dual-Phase VDD Control in 28-nm CMOS," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 12, pp. 4774-4783, Dec. 2020.
L. -Y. Yeh, P. -J. Chen, C. -C. Pai and T. -T. Liu, "An Energy-Efficient Dual-Field Elliptic Curve Cryptography Processor for Internet of Things Applications," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 67, no. 9, pp. 1614-1618, Sept. 2020.
C. -Y. Hong and T. -T. Liu, "A Variation-Resilient Microprocessor With a Two-Level Timing Error Detection and Correction System in 28-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 55, no. 8, pp. 2285-2294, Aug. 2020.
Z. -Y. Liang, H. -H. Wei and T. -T. Liu, "A Wide-Range Variation-Resilient Physically Unclonable Function in 28 nm," in IEEE Journal of Solid-State Circuits, vol. 55, no. 3, pp. 817-825, March 2020.
C. -Y. Ku and T. -T. Liu, "A Voltage-Scalable Low-Power All-Digital Temperature Sensor for On-Chip Thermal Monitoring," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 10, pp. 1658-1662, Oct. 2019.
F. Y. Xie, B. C. Wu, and T.-T. Liu, “A Ripple Reduction Method for Switched-Capacitor DC-DC Voltage Converter Using Fully Digital Resistance Modulation,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 9, pp. 3631-3641, Sept. 2019.
S. Y. Chang, B. C. Wu, Y. L. Liou, R. X. Zheng, P. L. Lee, T. D. Chiueh, and T.-T. Liu, “An Ultra-Low-Power Dual-Mode Automatic Sleep Staging Processor Using Neural-Network-Based Decision Tree,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 9, pp. 3504-3516, Sept. 2019.
B. C. Wu and T.-T. Liu, “Circuit Sensing Techniques in Magnetoresistive Random-Access Memory,” in Journal of Low Power Electronics, vol.14, no.2, pp. 206-216, June 2018.
T.-S. Chen, D.-Y. Lee, T.-T. Liu, and A.-Y. Wu, “Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol.63, no.10, pp.1661, Oct. 2016.
T.-T. Liu and J. Rabaey, “A 0.25V 460nW Asynchronous Neural Signal Processor with Inherent Leakage Suppression,” IEEE Journal of Solid-State Circuits, vol.48, no.4, pp.897-906, Apr. 2013.
D. Marković, C. C. Wang, L. Alarcón, T.-T. Liu , and J. Rabaey, “Ultra-Low Power Design in Near-Threshold Regime,” Proceedings of the IEEE, vol.98, no.2, pp.237–252, Feb. 2010.
T.-T. Liu, L. Alarcón, M. Pierson, and J. Rabaey, “Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.17, no.7, pp.883-892, Jul. 2009.
L. Alarcon, T.-T. Liu, M. Pierson, and J. Rabaey, “Exploring Very Low-energy Logic: A Case Study,” Journal of Low Power Electronics, vol.3, no.3, pp.223-233, Dec. 2007.

Conference & proceeding papers:

J. -C. Liu and T. -T. Liu, "Multi-Robot Formation Control using Collective Behavior Model and Reinforcement Learning," 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 2022, pp. 2261-2265.
B. -C. Wu and T. -T. Liu, "A Fully Integrated Switched-Capacitor Voltage Regulator with Multi-Rate Successive Approximation Achieving 190 ps Transient FoM and 83.7% Conversion Efficiency," 2021 Symposium on VLSI Circuits, 2021, pp. 1-2.
T. Wang and T.-T. Liu, "ECC processor over the Koblitz curves with τ-NAF Converter and Square-Square-Add Algorithm," 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2020, pp. 23-26.
C. H. Lee, Y. T. Hsu, T.-T. Liu, and T. D. Chiueh, "Design of an 45nm NCFET Based Compute-in-SRAM for Energy-Efficient Machine Learning Applications," 2020 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2020, pp. 193-196.
B.-C. Wu and T.-T. Liu, "Variation-Resilient Design Techniques for Energy-Constrained Systems," 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), Rhodes, Greece, 2019, pp. 228-231.
C. H. Wu, T. S. Chen, D. Y. Lee, T.-T. Liu, and A. Y. Wu, “Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine,” IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT’17), pp.1-4, April 2017.
T. S. Chen, D. Y. Lee, T.-T. Liu, and A. Y. Wu, "Filter-based dual-voltage architecture for low-power long-word TCAM design," 2nd IEEE International Conference on Intelligent Green Building and Smart Grid (IGBSG’16), pp. 1-5, June 2016.
C.-M. Huang, T.-T. Liu, and T-D. Chiueh, “An Energy-Efficient Resilient Flip-Flop Circuit with Built-In Timing-Error Detection and Correction,” IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT’15), pp.1-4, Apr. 2015
J. Ryckaert, P. Raghavan, R. Baert, M.G. Bardon, M. Dusa, A. Mallik, S. Sakhare, B. Vandewalle, P. Wambacq, B. Chava, K. Croes, M. Dehan, D. Jang, P. Leray, T.-T. Liu, K. Miyaguchi, B. Parvais, P. Schuddinck, P. Weemaes, A. Mercha, J. Bommels, N. Horiguch, “Design Technology Co-optimization for N10,” IEEE Proceedings of the Custom Integrated Circuits Conference (CICC’14), pp.1-8, Sept. 2014
A. Mallik, P. Zuber, T.-T. Liu, B. Chava, B. Ballal, P. Royer, K. Croes, B. Rogier, R. Julien, A. Mercha, M. Badaroglu, and D. Verkest, “TEASE: A Systematic Analysis Framework for Early Evaluation of FinFET-based Advanced Technology Nodes,” 50th ACM/EDAC/IEEE Design Automation Conference (DAC’13), pp. 1-6, Jun. 2013
J. Richmond, M. John, L. Alarcón, W. Zhou, W. Li, T.-T. Liu, M. Alioto, S. Sanders, and J. Rabaey, “Active RFID: Perpetual Wireless Communications Platform for Sensors,” Proceeding of the 38th European Solid-State Circuits Conference, 2012. (ESSCIRC’12), pp. 434-437, Sept. 2012
T.-T. Liu and J. Rabaey, “A 0.25V 460nW Asynchronous Neural Signal Processor with Inherent Leakage Suppression,” IEEE Symposium on VLSI Circuits (VLSIC’12), pp. 158-159, Jun. 2012
T.-T. Liu and J. Rabaey, “Statistical Analysis and Optimization of Asynchronous Circuits,” 18th IEEE International Symposium on Asynchronous Circuits and Systems, (ASYNC'12), pp. 1-8, May 2012
L. Alarcón, T.-T. Liu, and J. Rabaey, “A Low-Leakage Parallel CRC Generator for Ultra-Low Power Applications,” Proceedings of 2011 IEEE International Symposium on Circuits and Systems (ISCAS’11), pp.2063-2066, May 2011
T.-T. Liu and J. Rabaey, “Linearity Analysis of CMOS Passive Mixer,” Proceedings of 2011 IEEE International Symposium on Circuits and Systems (ISCAS’11), pp.2833-2836, May 2011
T.-T. Liu, L. Alarcón, M. Pierson, and J. Rabaey, “Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic,” 14th IEEE International Symposium on Asynchronous Circuits and Systems, (ASYNC '08), pp.105-115, Apr. 2008

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