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Project 1 (Completed)
Design and proposal of Area-scaled Nanosheet Tunnel FET for low-power applications
Objectives
Design of a Field-effect Transistor at a 5nm technology node for improved performance considering subthreshold swing and enhanced channel controllability for low-power applications.
Results
While considering the low power demand as a fundamental bottleneck for nanoscale devices, this work comprehensively investigates a novel concept that incorporates the area-scaled tunneling in a nanosheet field effect transistor (NSFET) at a 5-nm technology node. Integrating the area scale tunneling phenomenon with NSFET provides improved electrical performance. We observed ~50× improvement in drain current and ∼2× improvement in subthreshold slope (SS) by incorporating an epitaxial layer over the source region underneath the gate. Furthermore, 100 mV of the shift in tunneling onset voltage (VT, ON) is also noted when source doping increases from 1 × 1018 to 1 × 1020 cm-3. The gate-source overlap (LOV) significantly improves the transconductance without sacrificing the output resistance. It is examined that epitaxial layer thickness (TEPI) of 3-4 nm gives the best possible drive current for the proposed device. However, the OFF current exhibits an inversely proportional relation with TEPI. It is worth highlighting that optimum TEPI can be determined by only considering the suitable epitaxial layer doping profile (NEPI). A linear shift in VT, ON of the proposed device with work function (WF) is also reported in our work. Finally, the concept of multiple stacking is explored to boost the device’s performance. Including the presented device design guidelines, the ION/IOFF ratio of ∼4.5 × 108 with an average SS of ∼20 mV/dec is successfully demonstrated for the proposed device.
Project 2 (Completed)
Performance evaluation of ferroelectricity in spacer material of Si/SiGe hetero-junction Line-TFETs.
Objectives
Impact of Ferro-electricity in Spacer on the electrical performance of Si/SiGe Hetero-Junction Line TFETs.
Results
In this project, we have investigated the impact of ferroelectricity of high- κ spacers on the electrical performance of line-tunnel field-effect transistors (L-TFETs) by numerical simulation using technology computer-aided design (TCAD). We observed that the ferroelectric (FE) spacer increases the fringing electric field near the tunneling cross section at the source–epitaxial layer junction. This, in turn, increases the band-to-band tunneling (BTBT) generation and hence the drive capability of the device. Almost 2× improvement in the drive capability of L-TFET is observed when the saturation (Ps) and remanent polarization (Pr) of spacer material are kept at 60 and 3μC /cm2, respectively, without any significant change in the OFF current. A change of ∼ 100 mV in the tunneling onset voltage is also observed when Pr is increased from 1 to 3μC/cm2. A higher value of Pr results in increasing IOFF due to the onset of BTBT at zero gate bias. A ∼103× increase in IOFF is noted when Pr is increased beyond 3μC/cm2. A change of 40 mV in the saturation voltage was also noted when Ps was increased from 10 to 60μC/cm2. We have also observed a significant change in the device’s transconductance (gm) and output resistance (ro) with the variation in ferroelectricity of the spacer material. The gate capacitances also change with Ps and Pr, hence the bandwidth.
Project 3 (Completed)
Optimization of Epitaxial-Layer Based Hetero-junction Area Scaled Tunnel FET Label-Free Biosensors
Objectives
Performance Optimization of Epitaxial-Layer Based Si/SiGe Hetero-junction Area Scaled Tunnel FET Label-Free Biosensors Considering Steric Hindrance
Results
In this project, we explored Si/SiGe hetero-junction dielectrically modulated area-scaled tunnel FET (DM-ASTFET) for label-free bio-sensing applications. The proposed sensor can detect bioanalytics such as protein, APTES, Choline Oxidase and Uricase. We have also investigated the influence of quantum confinement on the proposed device, and the onset voltage shifted by 0.1–0.3 V, as reported, without affecting the sensitivity mechanism. Sensitivity improvement is observed when the gate oxide length is 20 nm, and the cavity length is 50 nm for a given bio-molecule due to the increased cross-section area for tunneling. The impact of epitaxial engineering on the biosensor's performance is also investigated in this work. A physics-based, in-depth explanation of steric hindrance on the performance of the proposed sensor is also presented in this work. Finally, the optimum device design improves the sensitivity of ION ∼×103 and Vth ∼×2 times.
Project 4 (ongoing)
Investigation of Field-Free Switching of 2-D Material-Based Spin-Orbit Torque Magnetic Tunnel Junction
Objectives
Enhancing performance of spintronic devices for data processing applications by limiting the static power consumption and enabling high-speed data transfer between on-chip memory and CPU.
Results
Spin Hall-assisted magnetization switching in a three-terminal magnetic tunnel junction (MTJ) has attracted much attention due to its high-speed magnetization switching, which enables low-power memory and logic applications. In this project, 2-D materials with high spin-orbit coupling (SOC) effects and high charge-to-spin conversion efficiency are used to assess the performance characteristics of spin-orbit torque MTJ (SOT-MTJ). External field-free switching in SOT-MTJ is accomplished by employing a standard MTJ structure with a bias magnetic layer on top of the structure that projects a dipolar magnetic field onto a free layer (FL). In addition, the Dzyaloshinskii–Moriya interaction (DMI), an asymmetric exchange interaction, is considered while evaluating the critical current density. We were able to demonstrate that the required critical current density decreases by 99.5%, while the switching speed increases by 86.67% in the proposed external field-free 2-D material-based SOT-MTJ. We have also shown the significance of DMI in the field-free switching of the magnetization without the requirement for additional mechanisms when the device shrank down to the sub-nanometer regime.
Project 4 (ongoing)
Comprehensive Performance Investigation of Back Gate Biasing
Objectives
Comprehensive Investigation of Back Gate Biasing on Performance of Line TFETs
Results
In this work, a physics-based comprehensive investigation of back gate biasing (VBS) on the performance of heterojunction Si/SiGe Line Tunnel FETs (L-TFET) is presented. The drain current (ID) increases with the reverse VBS, and then it saturates. The reverse VBS at which the drain current attains a maximum is defined as VBSAT, and it changes almost linearly with the gate bias (VGS). An incremental change in subthreshold slope and OFF-current is observed for the target device. Further, VDSAT slightly reduces with an increase in the reverse VBS. We observed a shift of 0.2 – 0.4 V in the value of onset voltage with quantum confinement with different reverse VBS. An increase in the drain current after the inclusion of the tensile strain profile was also observed with back gate biasing.
Publications
Journal Papers
S. Srivastava, S. Panwar and A. Acharya, "Proposal and Investigation of Area Scaled Nanosheet Tunnel FET: A Physical Insight," in IEEE Transactions on Electron Devices, vol. 69, no. 8, pp. 4693-4699, Aug. 2022, doi: 10.1109/TED.2022.3184915.
S. Panwar, S. Srivastava, M. Shashidhara and A. Acharya, "Performance Evaluation of High-κ Dielectric Ferro-Spacer Engineered Si/SiGe Hetero-Junction Line TFETs: A TCAD Approach," in IEEE Transactions on Dielectrics and Electrical Insulation, vol. 30, no. 3, pp. 1066-1071, June 2023, doi: 10.1109/TDEI.2023.3266413.
Sourabh Panwar, Shobhit Srivastava, Shashidhara M., Deepak Joshi, Abhishek Acharya, Performance optimization of epitaxial-layer based Si/SiGe hetero-junction area scaled tunnel FET label-free biosensors considering steric hindrance, Solid-State Electronics, Volume 210, 2023, 108810, ISSN 0038-1101, https://doi.org/10.1016/j.sse.2023.108810.
M. Shashidhara, V. Nehra, S. Srivastava, S. Panwar and A. Acharya, "Investigation of Field-Free Switching of 2-D Material-Based Spin-Orbit Torque Magnetic Tunnel Junction," in IEEE Transactions on Electron Devices, vol. 70, no. 3, pp. 1430-1435, March 2023, doi: 10.1109/TED.2023.3237654.
Shobhit Srivastava, M. Shashidhara, Sourabh Panwar, Shivendra Yadav, Abhishek Acharya, Understanding the Impact of Extension Region on Stacked Nanosheet FET: Analog Design Perspective, Solid-State Electronics, Volume 208, 2023, 108758, ISSN 0038-1101, https://doi.org/10.1016/j.sse.2023.108758.
M. Shashidhara, Shobhit Srivastava, Sourabh Panwar, Abhishek Acharya, Spin-orbit torque magnetic tunnel junction based on 2-D materials: Impact of bias-layer on device performance, Solid-State Electronics, Volume 208, 2023, 108757, ISSN 0038-1101, https://doi.org/10.1016/j.sse.2023.108757.
Yadav, A.K., S. Panwar, S. Srivastava, S. et al. Performance Analysis of III-V Hetero/Homojunction TFETs: an Analog Circuit Design Perspective. Silicon 14, 12525–12539 (2022). https://doi.org/10.1007/s12633-022-01889-z.
Conference Papers
S. Panwar, S. Srivastava, S. M, P. Dubey, D. Joshi and A. Acharya, "Comprehensive Investigation of Back Gate Biasing on Performance of Line TFETs," 2023 Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, 2023, pp. 81-82, doi: 10.23919/SNW57900.2023.10183969.
S. Srivastava, S. Panwar, S. M., N. Bagga, D. Joshi and A. Acharya, "Performance Investigation of Source/Drain Extension Region on Nanosheet FET: A Digital Design Perspective," 2023 Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, 2023, pp. 79-80, doi: 10.23919/SNW57900.2023.10183928.
Sourabh Panwar, Shobhit Srivastava, Shashidhara M., Deepak Joshi, Abhishek Acharya, "Performance optimization of epitaxial-layer based Si/SiGe hetero-junction area scaled tunnel FET label-free biosensors considering steric hindrance," in 9th Joint International Workshop and International Conference on EuroSOI-ULSI 2023, Tarragona, Spain, 2023, https://wwwa.fundacio.urv.cat/congressos/public/docs/abstract-euro-soi-2_1.pdf
Shobhit Srivastava, Shashidhara M, Sourabh Panwar, Shivendra Yadav, Abhishek Acharya, "Understanding the Impact of Extension Region on Stacked Nanosheet FET: Analog Design Perspective," in 9th Joint International Workshop and International Conference on EuroSOI-ULSI 2023, Tarragona, Spain, 2023, https://wwwa.fundacio.urv.cat/congressos/public/docs/abstract-euro-soi.pdf
C. Yeswanth, S. Panwar, S. Srivastava, D. Joshi, S. M and A. Acharya, "Configurable 8T SRAM-based Computing In- Memory Architecture for Enabling Shift Operation and Multibit Dot-Product Engines," 2023 IEEE Devices for Integrated Circuit (DevIC), Kalyani, India, 2023, pp. 330-334, doi: 10.1109/DevIC57758.2023.10134803.
A. K. Gupta, S. Panwar, et al., "9T SRAM Cell for Computation-In-Memory Architectures: Proposal & Investigation," 2023 IEEE Devices for Integrated Circuit (DevIC), Kalyani, India, 2023, pp. 282-286, doi: 10.1109/DevIC57758.2023.10134934.
Book Chapters
A Acharya, S Panwar, S. Srivastava, M Shashidhara, "Chapter-8: Epitaxial Layer‐Based Si/SiGe Hetero‐Junction Line Tunnel FETs: A Physical Insight" of the book "Advanced Ultra Low‐Power Semiconductor Devices: Design and Applications," at 165-186, of Wiley in 2023.
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