SPARC Workshop (February 2026)

A Workshop on

"RISC-V Processors and Neuromorphic Computing: Shaping the Future of Computing"

10 Feb - 12 Feb 2026

Distinguished Speakers:

Prof. Jayasimha Atulasimha (VCU, USA )

Mr. Sanjay Churiwala (Corporate Vice President, AMD, India )

Mr. Krishnakumar Rao S (Senior Director, C-DAC Trivandrum, India)

Mr. Libin T T (Associate Director, C-DAC Trivandrum, India)

Mode of delivery: Physical only (Venue: ECE Dept., IIT Roorkee)

Course Coordinators: Prof. Bishnu Prasad Das and Prof. Tanmoy Pramanik

In Memory of (Late) Prof. B.K. Kaushik

Dr. Brajesh Kumar Kaushik was a distinguished researcher and an inspiring educator whose contributions to the fields of nanoelectronics, VLSI design, and optoelectronic systems have significantly advanced our technical knowledge. His relentless pursuit of knowledge and innovation is evident in his extensive body of research, which has earned global recognition and enriched the academic community. As a professor at IIT Roorkee, he has nurtured many young minds, fostering a culture of excellence and curiosity. Dr. Kaushik will also be a guiding light for students and researchers. His dedication to pushing the boundaries of technology continues to inspire future generations, leaving an indelible mark on the world of electronics and communication engineering.

Overview

The workshop “RISC-V Processors and Neuromorphic Computing: Shaping the Future of Computing” offers a focused introduction to spintronics and emerging computing paradigms, neuromorphic and reservoir computing, reliable digital hardware design, and modern processor and SoC architectures. It connects device-level innovations with architecture- and system-level design to provide a unified view of next-generation computing hardware. Participants will gain insights into spintronic devices for neuromorphic, reservoir, and quantum computing, alongside essential concepts in digital design reliability, including clock domain crossing and synchronization. The workshop further covers RISC-V instruction set architecture, advanced pipelined, superscalar, and out-of-order processor designs, and FPGA versus ASIC design methodologies. The program concludes with in-depth sessions on VEGA processor architectures and VEGA processor–based SoC design, including practical exposure to system integration workflows. Overall, the workshop equips participants with both theoretical understanding and practical design perspectives required for future-ready computing systems.

Objectives

The primary objectives of the course are as follows :

To provide a comprehensive foundation in spintronic devices and emerging computing paradigms, covering the physical principles, device operation, and system-level implications of spin-based technologies for next-generation computing.
To introduce neuromorphic and reservoir computing frameworks using spintronic devices, enabling participants to understand brain-inspired computation, nonlinear dynamics, temporal processing, and their relevance to energy-efficient artificial intelligence.
To explore advanced applications of spintronics in emerging domains, including quantum computing and hybrid classical–quantum architectures, highlighting the role of spin-based devices in future information processing systems.
To strengthen participants’ expertise in reliable digital hardware design, with a focus on HDL-based methodologies, clock domain crossing, synchronization challenges, and best practices for robust system implementation.
To develop a solid understanding of modern processor architectures, encompassing RISC-V instruction set fundamentals, pipelined and superscalar microarchitectures, and out-of-order execution techniques for high-performance computing.
To familiarize participants with industry-relevant processor platforms and SoC design flows, through an in-depth study of VEGA processor architectures and hands-on experience in VEGA processor–based system-on-chip design.
To bridge theory and practice by integrating architectural concepts with real-world design workflows, empowering participants to analyze, design, and evaluate computing systems spanning devices, architectures, and complete SoC implementations.

Focus Areas

Fundamentals of spintronic devices and emerging computing technologies
Neuromorphic and reservoir computing using spintronic systems
Spintronics for quantum and beyond-CMOS computing paradigms
Reliable digital hardware design: CDC, synchronization, and HDL best practices
RISC-V–based processor architecture and advanced microarchitectures
FPGA vs. ASIC design methodologies and trade-offs
VEGA processor architectures and Full Hands-On SoC design
Product Life Cycle Session: From Idea to Working Product

Target Audience

This workshop is intended for BTech, MSc, MTech, and PhD students, faculty members, and practicing engineers from physics, electrical and electronics engineering, nanotechnology, and computer science, who are interested in spintronics and emerging computing paradigms, neuromorphic and reservoir computing, processor architecture and RISC-V, and reliable digital hardware design.
It will be particularly beneficial for participants seeking expertise in digital design reliability, clock domain crossing and synchronization, FPGA and ASIC platforms, and system-level hardware implementation.
The workshop is also relevant for researchers, engineers, and technical professionals from industry, R&D laboratories, startups, and government organizations working on processor architectures, SoC design, memory technologies, secure and reliable hardware systems, and next-generation computing platforms, including VEGA processor–based SoCs.
Industry professionals and decision-makers involved in emerging hardware technologies, processor and SoC development, and advanced computing systems will find the workshop valuable for gaining both theoretical insights and practical design perspectives.

Distinguished Speakers

Prof. Jayasimha Atulasimha

Virginia Commonwealth University (USA)

Official Webpage: Click Here

Mr. Sanjay Churiwala

Corporate Vice President,

AMD Telangana, India

Official Webpage: Click Here

Mr. Krishnakumar Rao S

Senior Director,

C-DAC Trivandrum, India

Official Webpage: Click Here

Mr. Libin T T

Associate Director,

C-DAC Trivandrum, India

Official Webpage: Click Here

Workshop Organizers

Prof. Bishnu Prasad Das

ECE Department Indian Institute of Technology Roorkee (India)

Official Webpage: Click Here

Prof. Tanmoy Pramanik

ECE Department Indian Institute of Technology Roorkee (India)

Official Webpage: Click Here

About SPARC

The Scheme for Promotion of Academic and Research Collaboration (SPARC), an initiative of Ministry of Human Resource Development, Government of India, aims at improving the research ecosystem of India’s higher educational institutions by facilitating academic and research collaborations between top ranked Indian Institutions and globally ranked Foreign Institutions, through Joint Research Projects involving mobility of students and faculty. The SPARC Scheme is expected to have a major impact in providing the best international expertise to address major national problems, expose Indian academicians to the best collaborators abroad, enable international faculty to stay in India for a longer duration, provide Indian students an opportunity to work in the world class laboratories, to develop strong bilateral relationships in research, and improve the international ranking of Indian Institutions.

About the Institute

The Indian Institute of Technology Roorkee has an illustrious history and a glorious past. It has its foundation as the Thomson College, which was founded in 1847, to train technical manpower for construction of Ganga canal. It was the first Engineering College in the then British Empire. In The year 1949, this great institution was accorded the status of the first technological university of independent India and was renamed as University of Roorkee. On September 21, 2001, the Government of India declared it as the Nation’s seventh Indian Institute of Technology.