Computer Organization and Architecture

This course would follow the RISC V micro-architecture. It would have two parts.

• The first looks at the RISC V ISA: Its support for programming languages and the support for Operating Systems.

• The second part discusses the processor micro-architecture and implementation aspects.

We would also have an associated lab, in which we will do RISC V based assembly coding.

INSTRUCTOR

Chester Rebeiro

TAS

• CS19D008 Praseetha M

• CS20D202 Pallavi Borkar

• CS20D408 Sai Venkata Krishnan V

• CS21D403 Saltanat Firdous Allaqband

• CS22D003 Ingale Kranti Bhimrao

• CS22M089 Swetha R

• CS23D008 Abdun Nihaal

• CS23D402 C Rohin Menon

• CS22M045 Chaudhari Gaurav Milind

• CS23M017 Arun R Bhat         

• CS23S002 Sudeep Chowdhary

• CS19B021 K V Vikram

• CS22M052 Koppela Harsha Vardhan Reddy

• CS20B013 Bersilin Robert

• CS20B031 Hemesh J

• CS20B035 Yaswanth Kandula

• CS20B069 Saran Kumar

LOGISTICS

The slides and assignments will be shared through Microsoft Teams (work or school).
Please create an account with your smail ID and join this team.

Classes will be held from 17th Jan, 2024 in Slot C at CS15 (CSE, IITM). Labs will be in P slot

• Monday : 10:00 - 10:50 AM

• Tuesday : 9:00 - 9:50 AM

• Wednesday : 8:00 - 8:50 AM

• Friday: 12:00 - 1:00PM (Tutorials)

• Labs: Monday 2:00 - 4:00 PM  

SCHEDULE

SLIDES

• First Day Handout

• Introduction to the Course

• Instruction Set Architecture for Programming Languages Support

• A simple single cycle microprocessor, peripherals, memory mapped-IO, and interrupts 

• Instruction Set Architecture for Operating Systems Support

• Accelerating Memory Operations: The Memory Hierarchy 

• CPU Pipelines and SupersScalar Organization