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Summary
Summary
For this board I connected two identical hex inverter circuits to a 555 timer output, but created a good layout for one circuit and a bad layout for the other. By monitoring quiet high and low lines for noise at synchronous switching edges of the timer circuit output, I gained valuable insights from analyzing and comparing their behaviors.
For this board I connected two identical hex inverter circuits to a 555 timer output, but created a good layout for one circuit and a bad layout for the other. By monitoring quiet high and low lines for noise at synchronous switching edges of the timer circuit output, I gained valuable insights from analyzing and comparing their behaviors.
Good vs. Bad Layout
Good vs. Bad Layout
Bad circuit layout is on the left, good layout is on the right
5V DC input gets regulated down to 3.3V using low drop out transistor
3.3V output feeds the supply voltage to the timer chip, as well as the quiet high test lines on the inverters
Test points were added to look at switching and instability noise on quiet lines, inverter/555 outputs, as well as the LDO 3V3 output and 5V rail.
Three Primary Issues
Three Primary Issues
Trace lengths are unnecessarily long
Decoupling capacitor C6 is far away from input on U2 pin 1
Lack of ground plane means some return paths are shared back to the bottom layer
Report
Report
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