Analog IC Design
0.35u CMOS Process IC Design of a PWM Module
Sawtooth Current Generator Subcircuit
Engineering Specifications:
DC Supply Voltage is Vdd = 3.3V
Control Signal vp is either 0V (L) or 3.3V (H)
Nominal Values of output current (Iout) at 27C and at Vo = 1.5V are as follows:
+1 uA +/- 5% for vp = 0V
-10 uA +/- 5% for vp = VDD
Over a range of 0.5V < Vo < 2.5V, output currents must be within +/- 0.5% of the nominal values obtained at Vo = 1.5V
Wide-swing cascode current mirrors must be implemented for high Bandwidth.
0.35u Process Constraints:
NMOS Body contacts shorted to most negative rail, PMOS Body contracts shorted to most positive rail
Transister widths and lengths may be as low as 0.35u but must increase as 1u, 2u, 3u, etc. Only in increments of 1u. There is no limit on number of transistors used.
RPN/RPP Resistors may not exceed 1mm in any dimension. These too, only have a resolution of 1u unless a minimum of 0.35u is chosen.
Discrete capacitors and WDIODE - 0.35u diodes may be implemented with area factors being only integer values.
"The best design is the one that meets specs and constraints while minimizing DC power consumption @27C for Vo = 1.5V"
To begin, I will implement a self-biased Vt-based current reference in the first stage. In the second-stage a CMOS inverter will determine which current mirrors will drive the current at Iout as seen in this figure:
After some preliminary circuit analysis and trial and error with the 0.35u CMOS Library in LTSpice, my final Design looks like this: (Analytical Hand Calculations Available upon Request)
Final Self-Biased Sawtooth Current Generator Circuit with Vp = 3.3V. Simulation current setup to sweep Vo and see affect on Iout. All Design Constraints Met per 0.35u CMOS Process Guidelines.
Specification 3:
Nominal Values of output current (Iout) at 27C and at Vo = 1.5V are as follows:
+1 uA +/- 5% for vp = 0V
-10 uA +/- 5% for vp = VDD
Verified Measurements:
Nominal Values of output current (Iout) at 27C and at Vo = 1.5V are as follows:
+1.004526 uA for vp = 0V (0.4526% Error) ✅
-10.01882 uA for vp = VDD (0.1882% Error) ✅
Specification 4:
Over a range of 0.5V < Vo < 2.5V, output currents must be within +/- 0.5% of the nominal values obtained at Vo = 1.5V
Verified Measurements:
Vp = 0, Ranges from 1.004508 to 1.004528 (at worst 0.0018% off from Vo = 1.5V Nominal Value)✅
Vp = 3.3, Ranges from -9.983216 to -10.0364 (at worst 0.3554% off from Vo = 1.5V Nominal Value) ✅
Bandwidth Response Iout/Vdd Biased at 3.3V
3dB cutoff frequency is 499 kHz and LF Gain is -103 dB. This is plenty low enough to suggest that small signal changes in Vdd do not have a transconductance amplification on the current output. There is also no resonance or Q-factor in the frequency response. Thus, this circuit is valid for a solid nominal 3.3V with low noise at any frequency.
Large-Signal Swing on Supply Rail Impact on Iout
Over a range of 0.5V < Vo < 2.5V, output currents must be within +/- 0.5% of the nominal values obtained at Vo = 1.5V
For Vp = 3.3V, output current will only be -9 to -11 uA in the narrow range of 3.162 to 3.44V. This design is not robust to large swings in VDD.
For Vp = 0V, output current will only be 0.9 to 1.1 uA for the similarly narrow range of 3.175 to 3.419V. Again, not robust to large swings in VDD.
Power Consumption
For Vp = 0V: 20.544 uW, For Vp = 3.3V: 17.229 uW