Speakers

Speakers:

Valentina Salapura is a Senior Fellow at AMD Research. Previously, she was a System Architect at the IBM T.J. Watson Research Center, and a faculty member at the Technische Universität Wien. Valentina is a computer architect for large computer systems, from supercomputers to cloud computing data centers. Valentina is a prolific inventor and holds more than 400 US patents, and she published a number of papers and several book chapters on processor and network architecture. Valentina was named Fellow of the Institute of Electrical and Electronics Engineers (IEEE) in 2012 for contributions to the architecture and design of multiprocessor systems, and is a recipient of the 2006 ACM Gordon Bell Prize for Special Achievements.

Alan Bivens,PhD. is currently the Director of Data Services, IBM Public Cloud, leading a variety of Cloud Data technologies including Cloud Databases, Object Storage, and Kafka offerings. Alan comes to this role after holding numerous senior management roles in IBM Research and Executive Staff positions in IBM’s Blockchain business unit. Alan is also a prolific writer with over 50 filed patents (earning him the distinction of being an IBM Master Inventor), and over 40 publications in the areas of cloud and distributed systems, systems management, and machine learning technologies.

Hyeran Jeon is an Assistant Professor in the CSE department at the University of California Merced. Her main research interests lie in energy-efficient, reliable, and high-performance computer architecture and systems design. Her research lab has been sponsored by the California Energy Commission, LAM Research, and Xilinx. She earned her Ph.D. at the University of Southern California. She has industry experience as an intern at IBM T.J. Watson Research Center and AMD Research, and as a systems software engineer at Samsung Electronics.

Panelists:

Shaizeen Aga is a Technical Lead and Member of Technical Staff at AMD Research where she leads a team focused on application-driven design of accelerators and future architectures. Her research interests include processor architectures, memory subsystems and security with a specific interest in near-memory accelerators. She obtained her Masters (2013) and Ph.D. (2017) from the University of Michigan, Ann Arbor and her research has been published at several top-tier computer architecture venues (ISCA, MICRO, HPCA) and also at high-performance computing venues (SC). Her research has won several awards at and across institutional level and she was an invited participant in Rising Stars in EECS, 2017 workshop. She is also a (co-)inventor on over 15 granted and pending US patents. She is passionate about mentoring and is the co-founder of Young Architect Workshop series which she co-organized at HPCA 2019 and ASPLOS 2020.

Caroline Trippel is an Assistant Professor in the Computer Science and Electrical Engineering Departments at Stanford University working in the area of computer architecture. Prior to starting at Stanford, Trippel spent nine months as a Research Scientist at Facebook in the FAIR SysML group. Her work focuses on promoting correctness and security as first-order computer systems design metrics (akin to performance and power). A central theme of her work is leveraging formal methods techniques to design and verify hardware systems in order to ensure that they can provide correctness and security guarantees for the applications they intend to support. Trippel's research has influenced the design of the RISC-V ISA memory consistency model both via her formal analysis of its draft specification and her subsequent participation in the RISC-V Memory Model Task Group. Additionally, her work produced a novel methodology and tool that synthesized two new variants of the now-famous Meltdown and Spectre attacks. Trippel's research has been recognized with IEEE Top Picks distinctions and the 2020 ACM SIGARCH/IEEE CS TCCA Outstanding Dissertation Award. She was also awarded an NVIDIA Graduate Fellowship (2017-2018) and selected to attend the 2018 MIT Rising Stars in EECS Workshop. Trippel completed her PhD in Computer Science at Princeton University and her BS in Computer Engineering at Purdue University.

Daniel J. Sorin is Professor of Electrical and Computer Engineering and of Computer Science at Duke University, where he has been on the faculty since 2002. He received a PhD and MS in electrical and computer engineering from the University of Wisconsin, and he received a BSE in electrical engineering from Duke University. He is the recipient of an NSF Career Award and the Imhoff Distinguished Teaching Award at Duke. He was a Visiting Fellow of the Royal Academy of Engineering (UK). His research interests are in computer architecture, with a focus on fault tolerance, verification, and memory system design. He is the author of “Fault Tolerant Computer Architecture” and a co-author of “A Primer on Memory Consistency and Cache Coherence.” He is the editor-in-chief of IEEE Computer Architecture Letters. He is a co-founder and Chief Architect at Realtime Robotics, Inc.

Muthulakshmi (Lakshmi) Muthukumarasamy is a Software Architect at Cadence Design Systems. Her research interests include computer architectures, hardware-software co-design and performance modeling. Her current work at Cadence focuses on software modeling, compiler and operating system technologies for Palladium Emulators. She received her MS and PhD from University of Kentucky in 2003 and 2010 respectively. She is a recipient of the UKY RCTF Fellowship (2005-2006), and has served in the Technical Committee as Co-Chair for Cadence Technical Conferences and in the Celebrations Committee for ACM-W-NA.

Russ Joseph is an Associate Professor of Electrical and Computer Engineering and Computer Science at Northwestern University, working in the areas of computer architecture, microprocessor design for reliability and variability tolerance and power-aware computing.

Panel Moderator:

Atefeh Mehrabi is a PhD candidate in the Electrical and Computer Engineering department at Duke University. She is co-advised by Prof. Daniel Sorin and Prof. Benjamin Lee. Her research is in the area of computer systems and architecture with a focus on design and management strategies for reconfigurable accelerators. She studies challenges of using modern techniques, such as high-level synthesis and partial reconfiguration, to design FPGA accelerators, and proposes solutions to simplify deploying FPGA accelerators at scale. Atefeh spent summer 2020 in Azure Hardware Architecture team at Microsoft and summer 2019 at Architecture Research Group at NVIDIA research as a research intern. She is also a 2019-2020 Cadence Women in Technology Scholarship recipient. She received her M. Sc degree in computer engineering from Duke University in 2018, and her B. Sc degree in electrical engineering from University of Tehran in 2016.