Abhinaya A

Assistant Professor in Computer Science & Engineering with 10+ years of experience across teaching, research, VLSI design, and technical mentoring. Experienced in curriculum development and delivery, laboratory instruction, student mentoring, project guidance, and research-oriented activities. Research interests span IoT, Embedded Systems, Intelligent Transportation Systems, and AI/ML applications. Scopus author and patent inventor, passionate about academic excellence, innovation, interdisciplinary research, and mentoring students to develop industry- and research-ready skills.

AREAS OF EXPERTISE

 Engineering Teaching & Student Mentorship

 Curriculum Design & Lab Planning

 C, C++, Data Structures Training, Bash Shell, Python (Basics)

 Digital Logic Design & RTL Fundamentals

 VLSI Design Flow (STA, Synthesis, P&R Basics)

 Placement Coordination, Interview Preparation & Evaluation

 Operating Systems: Linux, Windows

PATENTS, RESEARCH PUBLICATIONS, FDP’s & CERTIFICATIONS

·       Abhinaya A, “Smart pedestrian crossing bollard” Indian Patent Application No 202641092974, filed July 2026. Status: Pending.

·       Abhinaya A, Veena M. B, “Generation of Reduced Test Vectors for Multiple Stuck-at Faults using Genetic Algorithm”, International Journal of Innovative Technology and Exploring Engineering (IJITEE), Vol. 8, Issue 10, July 2019. [Scopus]

·       Faculty Development Programme (FDP): “Foundations of Effective Teaching and Soft Skills” – CMRIT, 1 Day, August 2026.

·       P3 Certification in C Programming – Department of Computer Science & Engineering, CMR Institute of Technology (CMRIT), August 2026.

ACADEMIC PROJECTS

·       Reduced Test Vector Generation for Multiple Stuck-at Faults using Genetic Algorithm (MTech Thesis) – Implemented GA-based ATPG method for multiple stuck-at fault detection using ISCAS benchmark circuits.

·       Low Power & Area Efficient Carry Select Adder (CSLA) – Designed modified CSLA at gate level reducing power and area while maintaining delay efficiency.

·       Adaptive Enhancement of Low Noise Amplifier (LNA) – Designed LNA using Cadence Virtuoso focusing on bandwidth and low-noise optimization.

·       Autonomous Vehicle Object Visualization – Implemented 2D/3D object visualization using KITTI data set and PCL library.

·       High Speed Parallel LFSR Architecture – Improved throughput for BCH/CRC encoding systems through state-space transformation method.

KEY ACHIEVEMENTS

·   Mentored 1,500+ students in C, C++, Data Structures (DSA), coding, and placement preparation.

·   Delivered placement-focused training, conducted mock technical/HR interviews, coding assessments, and interview preparation

·   Guided students in mini-projects, real-time projects, and hands-on lab sessions to strengthen coding, debugging, and problem-solving skills.

·   Supported placement coordination through student evaluation, shortlisting, performance tracking, and interview scheduling.

·   Contributed to Intel semiconductor design flow with STA analysis and optimization, while promoting industry-oriented learning and student mentoring.

·       Recognized for student-friendly teaching methods, strong mentoring approach, and ability to bridge the academic–industry skill gap