Embedded Files
Intended learning outcomes:
a) The Arithmetic and Logic Unit; ALU
Control Unit and Registers
- Program Counter; PC
- Accumulator; ACC
- Memory Address Register; MAR
- Memory Data Register; MDR
- Current Instruction Register; CIR
Buses: data, address and control: How this relates to assembly language programs.
b) The fetch-decode-execute cycle, including its effect on registers.
c) The factors affecting the performance of the CPU, clock speed, number of cores, cache.
d) The use of pipelining in a processor to improve.
e) Von Neumann, Harvard and contemporary processor architecture.
a) CPU Components
a) CPU Components
Videos
Videos
1.1.1a ALU, CU, Registers and Buses.mp4MegaProcessor - Computerphile.mp4b) The fetch-decode-execute cycle, including its effect on registers
b) The fetch-decode-execute cycle, including its effect on registers
Videos
Videos
1.1.1b Fetch decode execute cycle.mp4 c)The factors affecting the performance of the CPU, clock speed, number of cores, cache.
c)The factors affecting the performance of the CPU, clock speed, number of cores, cache.
d) The use of pipelining in a processor to improve.
d) The use of pipelining in a processor to improve.
Videos
Videos
e) Von Neumann, Harvard and contemporary processor architecture.
e) Von Neumann, Harvard and contemporary processor architecture.
Videos
Videos
1.1.1d Von Neumann and Harvard.mp4Exam Q&As
Exam Q&As
1.1.1_Structure_and_function_of_the_processor.pdf
Extra Resources
Extra Resources
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