Insights of Performance Enhancement techniques on High-Speed Computation Multiple 4-bit ALU (Journal of Technology)
2.DESIGN OF 3-BIT CMOS WALLACE MULTIPLIER
Patent
1.System and Method for enabling IOT based Drivers sleep
India Innovation Patent
https://drive.google.com/file/d/1bGTGTB2TNPiFkPZU1Ze8rTb9si7z3kfQ/view?usp=sharing
DESIGN PATENT PUBLISHED 2024
DESIGN PATENT PUBLISHED 2025
Paper published 2025
Presented paper in IEEE international conference 4th July 2025
Presented paper in IEEE international conference 24th Oct 2025