Mixed-signal Simulation Projects

Hardware Realization of Multi-Program Placement (Rectangle Filling)

Digital / RTL Design | Verilog, Synthesis & Timing Closure

Implemented a hardware accelerator for multi-program placement on a 128×128 compute array, translating a heuristic equifilling search algorithm into a fully pipelined RTL architecture with fixed 8-cycle end-to-end latency
Designed a strip-based placement architecture using LUTs, comparators, registers, and multiplexers to dynamically select target strips, update occupied widths, and detect strike conditions in real time
Achieved maximum clock frequency of 2.63 GHz, with area ≈ 3544 µm², energy ≈ 1.24×10⁻³ pJ per operation, and positive hold-time slack (0.04 ps) after synthesis and timing closure using SYNOPSYS EDA tools
Verified functional correctness against provided and hidden testbenches, ensuring cycle-accurate placement outputs and compliance with strict latency, area, and power constraints

Analog IC Design | Cadence Virtuoso (1.8 V CMOS)

Designed a fully differential NMOS-input folded-cascode OPAMP with common-mode feedback (CMFB), achieving 63.5 dB open-loop gain, 932 MHz UGBW, and 1.6 Vpp output swing under a 3 pF load
Optimized transistor sizing and bias currents to explore speed–power trade-offs, achieving 5.78 ns (1%) settling time at 14.8 mW and 20.05 ns settling at 5.5 mW
Derived and validated analytical models for gain error, loop stability, and large-signal settling behavior, verifying performance via DC, AC, and transient simulations in Cadence Virtuoso
Demonstrated spec-driven analog design methodology, balancing gain accuracy (<1% error), stability, and power efficiency across multiple operating points

Analog / Mixed-Signal IC Design Project – Cadence Virtuoso

Designed a 128×128 eDRAM memory array using 2T NN differential cells, supporting read/write operations with hierarchical decoding and sense amplification
Implemented row and column decoders (7-to-128 row decoding via 4-to-16 + 3-to-8 predecoders, 2-to-4 column decoding) to enable scalable and low-fanout memory addressing
Designed precharge circuits, differential sense amplifiers, low-power tristate buffers, and DFF-based registers to ensure reliable data sensing and output isolation
Integrated 4-to-1 multiplexers to reduce sense-amplifier count while supporting 32-bit read/write datapaths
Verified full memory functionality through transient simulations, achieving write delay = 0.435 ns, read delay = 1.422 ns, and correct data access across Row 0–127
Evaluated data retention and energy efficiency, measuring ~0.044 ns retention time, 0.022 nJ/bit write energy, and 0.023 nJ/bit read energy

RF / Analog IC Design Project (Cadence Virtuoso)

Designed a 2.4 GHz cascode CMOS LNA targeting WLAN applications, optimized for high gain, low noise figure, and stable 50 Ω matching under a 1.8 V supply
Performed topology comparison (CS, CG, Cascode) and selected inductively degenerated cascode architecture to balance gain, NF, linearity, and stability
Designed input matching network and source-degeneration feedback, analytically deriving and tuning inductors to achieve S11 < −10 dB across 2.40–2.48 GHz
Optimized bias current and transistor sizing via parametric sweeps to maximize gm·Cgs, achieving NF = 1.26–1.32 dB across the WLAN band
Designed output matching network for 50 Ω load and integrated bias, DC feed, and AC coupling to maximize power transfer and bandwidth
Verified performance through S-parameter, noise, and harmonic balance simulations, achieving 23.6 dB gain, 350 MHz bandwidth @ 2.44 GHz, and IIP3 = −9.17 dBm

Analog/Mixed-Signal IC Design (Cadence Virtuoso)

Designed and simulated a 10-bit segmented current-steering DAC targeting high-speed, high-linearity operation with a 50 Ω load at up to 500 MS/s
Evaluated and compared potentiometric vs. segmented DAC architectures, selecting a 6-bit thermometer + 4-bit binary-weighted topology to reduce glitch energy, parasitics, and area
Implemented custom CMOS logic blocks (INV, NAND, NOR), thermometer decoder, local decoders, and differential master–slave latches to ensure monotonic switching and timing robustness
Designed cascoded NMOS current source cells and differential switch drivers, achieving stable current steering with reduced output swing (~0.8–1.8 V) to minimize charge feedthrough
Integrated the full 10-bit DAC system and verified functionality in Cadence testbenches at 500 MS/s and 1 GS/s, including transient, INL, and SFDR simulations
Achieved INL < 0.125 LSB across the output range in post-simulation, validating static linearity and segmentation effectiveness

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