Chip & Design Gallery

ProCamo: A Fast Post-Manufacturing Programmable Camouflaged Logic Family 

Advances in semiconductor scaling and integration have increased design complexity,  concentrating valuable IP in single chips. Reverse engineering using high-resolution microscopy techniques,  such as scanning electron microscopy   (SEM)   and transmission electron microscopy (TEM),  enables detailed circuit analysis and extraction of layout-level information. At the same time, reliance on external foundries increases the risks of design information leakage.  To address these challenges, we propose a Fast Post-Manufacturing Programmable  Camouflaged  (FP2C)  Logic  Family,  which consists of physically identical logic structures that are activated by applying a post-programming code (PC) after fabrication. The proposed FP2C logic-embedded Flip-Flop (FP2C logic-eFF) was implemented using a 28nm CMOS process, achieving a 67% reduction in cell area compared to prior Post-Manufacturing Programmed Threshold Voltage Defined (PMP-TVD) logic cells on the same technology node. Furthermore, this paper presents a systematic design methodology that integrates FP2C logic-eFF into an EDA tool-based digital circuit design flow. This enables FP2C logic to move beyond prior camouflaged logic that was limited to full-custom arithmetic unit implementations,  and extend to complex digital IPs. To validate its feasibility, an AES module was designed and its functionality was verified through SPICE simulation, thereby demonstrating the applicability of FP2C logic to complex digital modules

S. Kim, M. Jeong, J. Lee, “ProCamo: A Fast Post-Manufacturing Programmable Camouflaged Logic Family,” IEEE/ACM Design, Automation and Test in Europe (DATE), Apr. 2026.

Synthesizable PUF Design with Library Characterization for Secure Storage in Edge Devices 

This work presents a synthesizable physically unclonable function (PUF) with library characterization that enables stable and secure key generation (KG) for edge-device storage. By combining sample-and-hold inverter-chain with digital tilting, masking,  and optional temporal majority voting  (TMV),  the proposed design achieves  low bit flip rate  (BFR)  under environmental variations and integrates with advanced encryption standard (AES) with only 5.72% area overhead. The results verify robust stability, uniqueness, and randomness, demonstrating its practicality for hardware-based secure storage.

Y. Lee, J. H. Kim, J. Lee, “Synthesizable PUF Design with Library Characterization for Secure Storage in Edge Devices,” IEEE/ACM Design, Automation and Test in Europe (DATE), Apr. 2026.

ProCamo: A Fast Post-Manufacturing Programmable Camouflaged Logic Family 

Advances in semiconductor scaling and integration have increased design complexity,  concentrating valuable IP in single chips. Reverse engineering using high-resolution microscopy techniques,  such as scanning electron microscopy   (SEM)   and transmission electron microscopy (TEM),  enables detailed circuit analysis and extraction of layout-level information. At the same time, reliance on external foundries increases the risks of design information leakage.  To address these challenges, we propose a Fast Post-Manufacturing Programmable  Camouflaged  (FP2C)  Logic  Family,  which consists of physically identical logic structures that are activated by applying a post-programming code (PC) after fabrication. The proposed FP2C logic-embedded Flip-Flop (FP2C logic-eFF) was implemented using a 28nm CMOS process, achieving a 67% reduction in cell area compared to prior Post-Manufacturing Programmed Threshold Voltage Defined (PMP-TVD) logic cells on the same technology node. Furthermore, this paper presents a systematic design methodology that integrates FP2C logic-eFF into an EDA tool-based digital circuit design flow. This enables FP2C logic to move beyond prior camouflaged logic that was limited to full-custom arithmetic unit implementations,  and extend to complex digital IPs. To validate its feasibility, an AES module was designed and its functionality was verified through SPICE simulation, thereby demonstrating the applicability of FP2C logic to complex digital modules

S. Kim, M. Jeong, J. Lee, “ProCamo: A Fast Post-Manufacturing Programmable Camouflaged Logic Family,” IEEE/ACM Design, Automation and Test in Europe (DATE), Apr. 2026.

A Synthesizable Thyristor-Like Leakage-Based True Random Number Generator

Accurate and efficient depth estimation from time-of-flight (ToF) LiDAR is essential for autonomous systems operating in real-world environments. However, traditional histogram-based depth estimation (HBDE) algorithms face fundamental limitations in balancing depth performance and computational cost, and they struggle under signal-induced pile-up distortion. While deep learning has shown promise, existing neural network-based methods rely on large models that are impractical for deployment on edge hardware. To bridge this critical gap, we propose a paradigm shift in histogram-based ToF estimation, reframing depth estimation from signal filtering to lightweight similarity learning. Instead of attempting to correct the distorted signal, our approach learns a specialized metric where the measure of similarity between the distorted histogram and a reference pulse is the temporal shift itself. The resulting 57.61 KB model, over 215.2× smaller than state-of-the-art deep learning approaches, achieves real-time performance (106.27 fps) on an FPGA. It delivers superior accuracy across nearly all signal-noise conditions, including 2.21 cm RMSE at severe pile-up scenarios, significantly outperforming conventional methods while remaining practical for on-device deployment.

M. Lee, S. H. Kim, Y. Park, H. Seo, J. Lee, “A Paradigm Shift in High-Resolution Depth Estimation Using SPAD-Based LiDAR Histograms: From Signal Filtering to Lightweight Similarity Learning,” AAAI Conference on Artificial Intelligence (AAAI), Jan. 2026.

A current-integrated differential NAND-structured PUF for stable and V/T variation-tolerant low-cost IoT security

We designed a current-integrated differential NAND-structured physically unclonable function (PUF) with lossless stabilization for cost-efficient IoT security. The area-efficient NAND array structure with 20F2 area per bit and lossless stabilization through remapping achieves both high cost efficiency and reliability. By utilizing the drain current (IDS) with near-threshold (near-VTH) bias, which is exponentially dependent on VTH, a pair of minimum-sized PMOS from the NAND array generated a stable response with a wide IDS mismatch. With the IDS integration, stability of a response is quantized to enable lossless stabilization through remapping. The proposed PUF achieved a bit error rate (BER) of 0.12% and an unstable bit rate (UBR) of 0.97% with remapping and TMV11. Also, supply voltage and temperature (V/T) variation immunities of 0.145%/0.1V and 0.120%/10℃, respectively, were observed, which represent 2.9×/2.5× improvements from an earlier NAND-structure PUF without stabilization. 

J. Lee, Y. Lee, “A current-integrated differential NAND-structured PUF for stable and V/T variation-tolerant low-cost IoT security ,” IEEE Asian Solid-State Circuits Conference (A-SSCC), Nov. 2021.

Jongmin. Lee, Minsun Kim, Minhyeok Jeong, Gicheol Shin, Yoonmyung. Lee, “A 20F2/bit Current-Integration-Based Differential NAND-Structured PUF for Stable and V/T Variation-Tolerant Low-Cost IoT Security” IEEE Journal of Solid-State Circuits (JSSC), Invited Paper to the Special Section on A-SSCC, Oct. 2022.

A 354F² Leakage-based Physically Unclonable Function with Lossless Stabilization Through Remapping for IoT Security

We revised a leakage-based physically unclonable function (PUF) with 354F2 area per bit to provide cost-effective security for IoT devices. By exploiting the exponential dependence of subthreshold leakage current on a transistor’s threshold voltage variations, a response key bit is generated with only 354F2 silicon area. Moreover, to improve stability without discarding Challenge-Response Pairs (CRPs), a novel lossless stabilization scheme called ‘remapping’ is proposed. The proposed leakage-based PUF exhibited a 3.87% native unstable bit ratio (UBR) and 0.426% native bit error rate (BER). With the proposed remapping and 11-bit temporal majority voting applied, the BER and UBR are significantly improved to 47 ppm and 538 ppm, respectively, achieving stability as high as a conventional trimming approach without any key losses. 

Jongmin Lee, Donghyeon Lee, Yongmin Lee, Yoonmyung Lee, “A 354F2 Leakage-Based Physically Unclonable Function with Lossless Stabilization through Remapping for Low-Cost IoT Security” IEEE Journal of Solid-State Circuits (JSSC), Feb. 2021.

An 20F² Area-Efficient Differential NAND-Structured Physically Unclonable Function for Low-Cost IoT Security

We designed a differential NAND-structured physically unclonable function (PUF) with 20F2 area per bit for cost-effective IoT applications. With the area-efficient NAND-array structure, a key bit is generated from a pair of minimum-sized NMOS transistors by effectively amplifying threshold voltage (Vth) mismatch. By utilizing the near-threshold current of the examined transistors, high sensitivity to Vth variation, which is desired for stability, and faster operation than leakage current based PUFs is achieved. An offset-compensated comparison scheme is provided to accurately determine the key value without bias. The proposed PUF achieves 0.06% BER and 0.53% unstable bits with TMV11 while reducing the area by an order of magnitude compared with state-of-the-art CMOS-based PUFs 

J. Lee, M. Kim, G. Shin, Y. Lee, “A 20F2 Area-Efficient Differential NAND-Structured Physically Unclonable Function for Low-Cost IoT Security ,” IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2019.

Jongmin Lee, Minsun Kim, Gicheol Shin, Yoonmyung Lee, “A 20F2 Area-Efficient Differential NAND-Structured Physically Unclonable Function for Low-Cost IoT Security ,” IEEE Solid-State Circuits Letters (SSC-L), Sep. 2019. (Cross-published)

A 445F² Leakage-based Physically Unclonable Function with Lossless Stabilization Through Remapping for IoT Security

We designed a leakage-based physically unclonable function (PUF) with 445F2 area per bit for low-cost IoT security. A lossless stabilization is achieved by novel remapping scheme where PUF cells in unstable challenge-response pairs (CRPs) are remapped to construct stable CRP, avoiding costly CRP loss in conventional trimming approach. Thanks to the lossless stabilization scheme, proposed PUF achieves 0.004% BER and 0.04% unstable cells with zero CRP loss by applying remapping for 10% of CRPs and TMV11.

J. Lee, D. Lee, Y. Lee, Y. Lee, “A 445F2 Leakage-Based Physically Unclonable Function with Lossless Stabilization through Remapping for IoT Security,” IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018.